Memory module decoder
View Patent ↗A memory module connectable to a computer system includes a printed circuit board, a plurality of memory devices coupled to the printed circuit board, and a logic element coupled to the printed circuit board. The plurality of memory devices has a first number of memory devices. The logic element receives a set of input control signals from the computer system. The set of input control signals corresponds to a second number of memory devices smaller than the first number of memory devices. The logic element generates a set of output control signals in response to the set of input control signals. The set of output control signals corresponds to the first number of memory devices.
1. A memory module connectable to a computer system, the memory module comprising:
a printed circuit board;
a plurality of memory devices coupled to the printed circuit board, the plurality of memory devices having a first number of memory devices; and
a logic element coupled to the printed circuit board, the logic element receiving a set of input control signals from the computer system, the set of input control signals corresponding to a second number of memory devices smaller than the first number of memory devices, the logic element generating a set of output control signals in response to the set of input control signals, the set of output control signals corresponding to the first number of memory devices, wherein the plurality of memory devices are arranged in a first number of ranks, and the set of input control signals corresponds to a second number of ranks of memory modules, the second number of ranks less than the first number of ranks, wherein the logic element further responds to a first command signal from the computer system by generating a second command signal transmitted to the plurality of memory devices, the first command signal corresponding to the second number of ranks and the second command signal corresponding to the first number of ranks.
2. The memory module of claim 1 , wherein the first command signal is a refresh signal or a precharge signal.
3. The memory module of claim 1 , wherein the memory devices comprise dynamic random-access memory (DRAM) devices.
4. The memory module of claim 1 , wherein the set of input control signals comprises a first number of chip-select signals and wherein the set of output control signals comprises a second number of chip-select signals, wherein the first number of chip-select signals is less than the second number of chip-select signals, the memory module simulating a virtual memory module having the second number of memory devices.
5. The memory module of claim 1 , wherein the logic element comprises an application-specific integrated circuit.
6. The memory module of claim 1 , wherein the logic element comprises a field-programmable gate array.
7. The memory module of claim 1 , wherein the logic element comprises a custom-designed semiconductor device.
8. The memory module of claim 1 , wherein the logic element comprises a complex programmable-logic device.
9. The memory module of claim 1 , wherein the first number of ranks is four, and the second number of ranks is two.
10. The memory module of claim 1 , wherein the first number of ranks is two, and the second number of ranks is one.
11. The memory module of claim 1 , wherein the set of input control signals comprises two chip-select signals and an address signal and the set of output control signals comprises four chip-select signals.
12. The memory module of claim 1 , wherein the printed circuit board is mountable in a module slot of the computer system, the printed circuit board having a plurality of edge connections electrically coupled to corresponding contacts of the module slot.
13. The memory module of claim 1 , wherein the plurality of memory devices are arranged to provide a first memory density per rank, and the set of output control signals corresponds to a second memory density per rank, the second memory density greater than the first memory density per rank.