Memory with high dielectric constant antifuses and method for using at low voltage
A memory array having memory cells comprising a diode and an antifuse can be made smaller and programmed at lower voltage by using antifuse materials having higher dielectric constant and higher acceleration factor than silicon dioxide, and by using diodes having lower band gaps than silicon. Such memory arrays can be made to have long operating lifetimes by using the high acceleration factor and lower band gap materials. Antifuse materials having dielectric constants between 5 and 27, for example hafnium silicon oxynitride or hafnium silicon oxide are particularly effective. Diode materials with band gaps lower than silicon, such as germanium or a silicon-germanium alloy are particularly effective.
1 . A memory cell for reliable low voltage reading and writing comprising:
a diode in series with an antifuse, the antifuse being made of one of X v Si w O x , X v O w and X v Si w O x N y , where X represents an element from the family consisting of La, Hf, Ta, Y, Zr, and Nb and the subscripts v, w, x, and y can have any values that form a stable compound.
2 . A memory cell for reliable low voltage reading and writing as in claim 1 , wherein the antifuse has a thickness between 20 and 65 angstroms.
3 . A memory cell for reliable low voltage reading and writing as in claim 1 , wherein the antifuse has a dielectric constant between 5 and 27.
4 . A memory cell for reliable low voltage reading and writing as in claim 1 , wherein the diode comprises a material having a band gap lower than that of silicon.
5 . A memory cell for reliable low voltage reading and writing as in claim 4 , wherein the band gap is lower than 1.1 electron volts.
6 . A memory cell for reliable low voltage reading and writing as in claim 4 , wherein the diode comprises a material from the group consisting of germanium (Ge) and any silicon-germanium alloy (Si x Ge 1-x ).
7 . A memory cell for reliable low voltage reading and writing as in claim 1 , wherein the memory cell is in an array of such memory cells.
8 . A memory cell for reliable low voltage reading and writing as in claim 7 , wherein the array of such memory cells is a monolithic 3-dimensional array in which the memory cells are formed in a plurality of memory cell levels in an integrated circuit device.
9 . A memory cell for reliable low voltage reading and writing comprising:
a diode in series with an antifuse, the antifuse being formed from a layer made of an insulating material having a dielectric constant in the range of 6 to 27; and
wherein the diode is formed from a semiconductor material with a band gap smaller than that of silicon.
10 . A memory cell for reliable low voltage reading and writing as in claim 9 , wherein the band gap is smaller than 1.12 electron volts.
11 . A memory cell for reliable low voltage reading and writing as in claim 9 , wherein the diode comprises a material from the group consisting of germanium (Ge) and a silicon germanium alloy (Si x Ge 1-x ).
12 . A memory cell for reliable low voltage reading and writing as in claim 9 , wherein the antifuse has a thickness between 20 and 65 angstroms.
13 . A memory cell for reliable low voltage reading and writing as in claim 9 , wherein the antifuse comprises a material taken from the family consisting of X v Si w O x , X v O w , and X v Si x O x N y , where X represents an element from the family consisting of La, Hf, Ta, Y, Zr, and Nb and the subscripts v, w, x and y can have any value that forms a stable compound.
14 . A memory cell for reliable low voltage reading and writing as in claim 9 , wherein the memory cell is formed of materials that can be programmed with a voltage less than 6 volts.
15 . A memory cell for reliable low voltage reading and writing as in claim 9 , wherein the diode comprises re-crystallized material.
16 . A memory cell for reliable low voltage reading and writing as in claim 9 , wherein the diode is formed from deposited material.
17 . A memory cell for reliable low voltage reading and writing as in claim 9 , wherein the diode is formed from a material that can be read using a bias voltage less than 2 volts.
18 . A method of forming and programming an array of memory cells each comprising an antifuse in series with a diode, the method comprising:
forming the antifuse from an insulator having a dielectric constant above 5;
forming the diode from a thin film semiconductor material with a band gap smaller than that of silicon;
programming a selected one of the memory cells by applying a voltage in a direction opposite that of natural current flow through the diode of the selected memory cell, the voltage being sufficient to short the antifuse.
19 . A method of forming and programming an array of memory cells as in claim 18 , further comprising
applying a second voltage to word lines contacting unselected ones of the memory cells; and
applying a third voltage to bit lines contacting the unselected ones of the memory cells, wherein the second and third voltages are substantially equal.
20 . A method of forming and programming an array of memory cells as in claim 19 , wherein the second and third voltages are approximately half the voltage applied to the selected one of the memory cells.
21 . A method of forming and programming a memory cell comprising an antifuse in series with a diode, the method comprising:
forming the antifuse from an insulator having a dielectric constant above 5,
forming the diode from a semiconductor material having a band gap smaller than that of silicon;
programming the memory cell by:
applying a first voltage in a direction of natural current flow through the diode, the first voltage being sufficient to short the antifuse; and
applying a second voltage in the direction of natural current flow through the diode, the second voltage being sufficient to cause current to pass through the shorted antifuse and to further reduce resistance of the shorted antifuse.
22 . A method of forming and programming a memory cell as in claim 21 , wherein the memory cell is a selected cell within an array of memory cells each contacting a bit line, at its anode end and a word line at its cathode end, the method further comprising:
applying the first voltage to word lines contacting unselected memory cells; and
applying a third voltage to bit lines contacting unselected memory cells that is lower than the first voltage.
23 . A method of forming and programming a memory cell as in claim 22 , wherein the third voltage is less than or equal to a threshold voltage of diodes in the memory cells.
24 . A method of forming and programming a memory cell as in claim 21 , wherein the second voltage is greater than the first voltage.
25 . A method of forming and programming a memory cell as in claim 21 , wherein the second voltage is less than the first voltage.
26 . In a memory comprising an array of memory cells, each memory cell comprising an antifuse in series with a diode, each memory cell having an anode end connected to an anode end of the diode and a cathode end connected to a cathode end of the diode, and each memory cell cathode end being connected to a word line and each memory cell anode end being connected to a bit line, a method of programming one of the memory cells comprising:
applying to a bit line connected to a selected one of the memory cells a voltage sufficient to short the antifuse of the selected one of the memory cells;
applying to a word line connected to the selected one of the memory cells a ground voltage;
applying to bit lines contacting the anode ends of memory cells not selected a voltage less than or equal to a threshold voltage of the diodes; and
applying to word lines contacting the cathode ends of memory cells not selected a voltage less than or equal to one threshold voltage below the voltage sufficient to short the antifuse of the memory cell.
27 . A method of programming one of the memory cells of claim 26 , wherein the antifuse has a dielectric constant between 6 and 27, and the diode is formed from a thin film material having a band gap smaller than that of silicon.
28 . A method of programming one of the memory cells of claim 27 , wherein the thin film material is a silicon germanium alloy.