IP Library Granted Patent US 7,193,698
Granted Patent B2
US 7,193,698 · App. 11/182,798 · Granted Mar 20, 2007

Wafer defect detection methods and systems

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Quick Facts
Patent No.
US 7,193,698
App. No.
11/182,798
Granted
Mar 20, 2007
Kind
B2
Abstract

A wafer detection method. A plurality of PSL particles are sprayed on a wafer. An inspection operation is implemented on the wafer to obtain location information corresponding to a plurality of defects on the wafer, each location information corresponding to the defects comprises an error value. An inspection operation implemented on the PSL particles to obtain location information corresponding to the PSL particles. Offset location information corresponding to each defect is calculated according to the location information corresponding to each PSL particle. The error values corresponding to each defect are corrected according to the offset location information corresponding to each defect.

Claims (23)

1. A wafer defect detection method, comprising:

spraying a plurality of locating particles on a wafer;

implementing an inspection operation on the wafer to obtain location information corresponding to a plurality of defects on the wafer, wherein each location information corresponding to the defects comprises an error value;

implementing an inspection operation on the locating particles to obtain location information corresponding to the locating particles;

calculating offset location information corresponding to each defect according to the location information corresponding to each locating particle; and

correcting error values corresponding to each defect according to the offset location information corresponding to each defect.

2. The wafer defect detection method as claimed in claim 1 , wherein the locating particles are PSL particles.

3. The wafer defect detection method as claimed in claim 1 , wherein the size of each defect size is less than 100 nm.

4. A wafer defect detection method, comprising:

spraying a plurality of locating particles on a wafer;

implementing an inspection operation on the wafer to obtain location information corresponding to a plurality of defects on the wafer, wherein each location information corresponding to the defects comprises an error value;

implementing an inspection operation on the locating particles to obtain location information corresponding to the locating particles;

calculating offset location information corresponding to error defect location and real defect location information relating to each defect according to the location information corresponding to each locating particle; and

correcting error values corresponding to each defect according to the offset location information.

5. The wafer defect detection method as claimed in claim 4 , wherein the locating particles are PSL particles.

6. The wafer defect detection method as claimed in claim 4 , wherein the size of each defect is less than 100 nm.

7. A wafer defect detection system, comprising:

a particle spraying unit, spraying a plurality of locating particles on a wafer;

a defect detection unit, coupled to the particle spraying unit, implementing an inspection operation on the wafer to obtain location information corresponding to a plurality of defects on the wafer, wherein each location information corresponding to the defects comprises an error value;

a particle detection unit, coupled to the defect detection unit, implementing an inspection operation on the locating particles to obtain location information corresponding to the locating particles; and

a particle re-detection unit, coupled to the particle detection unit, calculating offset location information corresponding to each defect according to the location information corresponding to each locating particle, and correcting error values corresponding to each defect according to the offset location information corresponding to each defect.

8. The wafer defect detection system as claimed in claim 7 , wherein the locating particles are PSL particles.

9. The wafer defect detection system as claimed in claim 7 , wherein the size of each defect is less than 100 nm.

Assignments (3)
CHANGE OF NAME Recorded Jul 16, 2019
From: POWERCHIP TECHNOLOGY CORPORATION
To: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
Reel/Frame 049757/0536 →
CHANGE OF NAME Recorded Jun 28, 2019
From: POWERCHIP SEMICONDUCTOR CORP.
To: POWERCHIP TECHNOLOGY CORPORATION
Reel/Frame 049629/0267 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2005
From: LIN, LONG-HUI; CHAN, LI-YU
To: POWERCHIP SEMICONDUCTOR CORP.
Reel/Frame 016763/0761 →