IP Library Granted Patent US 7,558,904
Granted Patent B2
US 7,558,904 · App. 11/187,650 · Granted Jul 7, 2009

Controller, data memory system, data rewriting method, and computer program product

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Quick Facts
Patent No.
US 7,558,904
App. No.
11/187,650
Granted
Jul 7, 2009
Kind
B2
Abstract

The controller of the present invention includes an address management table that stores address information of valid data among the data stored in a flash memory, a status flag stored in the flash memory indicating that the data before rewriting and the data after rewriting are in process of rewriting, and a data rewriting process unit (the data management means) that changes the address information of the valid data from the data before rewriting to the data after rewriting at a given timing. It is thus possible to specify an area in process of rewriting even if the power supply is stopped in process of rewriting. It is also possible to judge the valid data when the process is restarted from the power off and erase the unnecessary data.

Claims (47)

1. A controller for controlling writing of data into a semiconductor device comprising:

a data management unit creating first management information showing that first data that has been stored in the semiconductor device is in process of rewriting and second management information showing that second data to be newly written into the semiconductor device is in process of rewriting, wherein the data management unit comprising:

an address management table that stores address information on valid data; and

a rewriting process unit that stores the first and second management information at the time of rewriting and changes the address information on the valid data from address information on the first data to address information on the second data at a given timing.

2. The controller as claimed in claim 1 , wherein:

the first management information includes management information that shows the first data is valid until rewriting is completed; and

the second management information includes management information that shows the second data is set valid after rewriting is completed.

3. The controller as claimed in claim 1 , further comprising a part that writes the first management information and the second management information in the semiconductor device along with the first and second data.

4. The controller as claimed in claim 1 , further comprising a part that writes the address information on the valid data into another semiconductor device.

5. The controller as claimed in claim 1 , wherein the address management unit comprises an address management table that stores a virtual address associated with a physical address of valid data stored in the semiconductor device; and

the controller comprises a rewriting process unit that changes the physical address from a physical address of the first data to that of the second data at a given timing.

6. A controller for controlling writing of data into a semiconductor device comprising:

a data management unit creating first management information showing that first data that has been stored in the semiconductor device is in process of rewriting and second management information showing that second data to be newly written into the semiconductor device is in process of rewriting, wherein:

the first management information includes management information that shows the first data is valid until rewriting is completed, and the second management information includes management information that shows the second data is set valid after rewriting is completed;

the data management unit includes an address management table that stores address information on valid data; and

the controller includes a garbage collection unit that newly writes only valid data into another area in the semiconductor device by referring to the first management information and/or the second management information and the address management table.

7. A controller for controlling writing of data into a semiconductor device comprising:

a data management unit creating first management information showing that first data that has been stored in the semiconductor device is in process of rewriting and second management information showing that second data to be newly written into the semiconductor device is in process of rewriting, wherein:

the first management information includes management information that shows the first data is valid until rewriting is completed, and the second management information includes management information that shows the second data is set valid after rewriting is completed; the data management unit includes an address management table that stores address information on valid data; and

the controller includes a recovery unit that refers to the first management information and/or the second management information and the address management table when a supply of power to the semiconductor device stops during a rewriting process, and restarts rewriting on the basis of a status of progress of the rewriting process identified by the first management information and/or the second management information and the address management table.

8. A method of rewriting data into a semiconductor device comprising the steps of;

storing first management information showing that a memory area in the semiconductor device having first data to be replaced is in process of rewriting;

writing second data into another memory area; and

storing second management information showing that said another memory area is in process of rewriting, further comprising the steps of:

changing information registered in an address management table storing address information on valid data from address information on the first data to address information on the second data; and changing the second management information to third management information indicating completion of rewriting.

9. The method as claimed in claim 8 , further comprising the steps of:

detecting the first management information and/or the second management information;

determining whether data indicated by management information detected is registered in the address management table as valid data; and

newly writing only data registered as valid data into another area of the semiconductor device.

10. The method as claimed in claim 8 , further comprising the steps of:

identifying data in process of rewriting by referring to the first management information and/or the second management information when a supply of power to the memory stops during a rewiring process;

recognizing a status of progress of the rewriting process on the basis of management information referred to and valid data indicated by the address management table; and

restarting writing on the basis of the status of progress of the rewriting process.

11. A computer program product embodied in a computer readable storage medium and comprising computer instructions for causing a computer to execute the following steps of:

storing first management information showing that a memory area in the semiconductor device having first data to be replaced is in process of rewriting;

writing second data into another memory area; and

storing second management information showing that said another memory area is in process of rewriting, further comprising the steps of:

changing information registered in an address management table storing address information on valid data from address information on the first data to address information on the second data; and

changing the second management information to third management information indicating completion of rewriting.

12. The computer program product as claimed in claim 11 , further comprising the steps of:

detecting the first management information and/or the second management information;

determining whether data indicated by management information detected is registered in the address management table as valid data; and

newly writing only data registered as valid data into another area of the semiconductor device.

13. The computer program product as claimed in claim 11 , further comprising the steps of:

identifying data in process of rewriting by referring to the first management information and/or the second management information when a supply of power to the memory stops during a rewiring process;

recognizing a status of progress of the rewriting process on the basis of management information referred to and valid data indicated by the address management table; and

restarting writing on the basis of the status of progress of the rewriting process.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2021
From: CYPRESS SEMICONDUCTOR CORPORATION
To: LONGITUDE FLASH MEMORY SOLUTIONS LTD.
Reel/Frame 058346/0396 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 8, 2021
From: CYPRESS SEMICONDUCTOR CORPORATION
To: LONGITUDE FLASH MEMORY SOLUTIONS LTD.
Reel/Frame 058340/0069 →
RELEASE OF SECURITY INTEREST Recorded Sep 14, 2021
From: MUFG UNION BANK, N.A.,
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 057501/0144 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036044/0122 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 12, 2005
From: NAKAJIMA, ISAMU
To: SPANSION LLC
Reel/Frame 017086/0278 →