System and method for reducing cross-coupling noise between charge storage elements in a semiconductor device
View Patent ↗A memory device is provided including a substrate. A first dielectric layer is formed over the substrate. An isolation trench is formed in a portion of the substrate and the first dielectric layer. At least two charge storage elements are formed over the first dielectric layer on opposite sides of the isolation trench. A second dielectric layer is formed over the at least two charge storage elements. A control gate layer is formed over the second dielectric layer, where the isolation trench has a width suitable for reducing cross-coupling noise of charge storage elements, and where the at least two charge storage elements have a height suitable for providing sufficient gate coupling between the at least two charge storage elements and the control gate layer.
1. A memory device, comprising:
a substrate;
a first dielectric layer formed over the substrate;
an isolation trench formed in a portion of the substrate and the first dielectric layer;
at least two charge storage elements formed over the first dielectric layer on opposite sides of the isolation trench;
a second dielectric layer formed over the at least two charge storage elements; and
a control gate layer formed over the second dielectric layer,
where the isolation trench has a width suitable for reducing cross-coupling noise of charge storage elements,
where the at least two charge storage elements have a height suitable for providing sufficient gate coupling between the at least two charge storage elements and the control gate layer, and
where a ratio of isolation trench width to charge storage element height ranges from about 20:3 to about 30:1.
2. The memory device of claim 1 , where the width of the isolation trench ranges from about 1000 Å to about 3000 Å.
3. The memory device of claim 1 , where the at least two charge storage elements comprise polysilicon.
4. The memory device of claim 1 , where the height of the at least two charge storage elements ranges from about 30 Å to about 100 Å.
5. The memory device of claim 4 , where the width of the at least two charge storage elements ranges from about 500 Å to about 200 Å.
6. The memory device of claim 1 , further comprising
a field oxide layer formed in the isolation trench below the second dielectric layer.
7. The memory device of claim 6 , where an upper surface of the field oxide layer is above an upper surface of the first dielectric layer.
8. The memory device of claim 6 , where the height of the field oxide layer ranges from about 300 Å to about 900 Å.
9. The memory device of claim 1 , where the second dielectric layer comprises an oxide-nitride-oxide stack.
10. The memory device of claim 1 , where the control gate layer comprises polysilicon.
11. A memory device, comprising:
a tunnel oxide layer formed over a substrate;
a charge storage layer formed over the tunnel oxide layer; and
an isolation trench formed in a portion of the substrate, the isolation trench forming two charge storage elements on opposite sides of the isolation trench,
where a ratio of isolation trench width to charge storage element height ranges from about 20:3 to about 30:1.
12. The memory device of claim 11 , further comprising:
an inter-gate dielectric layer formed over the charge storage elements; and
a control gate layer formed over the inter-gate dielectric layer.
13. The memory device of claim 11 , where the charge storage elements comprise a conductive material having a height ranging from about 300 Å to about 900 Å.