IP Library Granted Patent US 7,378,740
Granted Patent B2
US 7,378,740 · App. 11/196,038 · Granted May 27, 2008

Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit

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Quick Facts
Patent No.
US 7,378,740
App. No.
11/196,038
Granted
May 27, 2008
Kind
B2
Abstract

An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the di-electric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.

Claims (12)

1. A dual damascene structure for electrically interconnection to a base metal interconnect structure formed in a semiconductor substrate, which comprises:

a first dielectric layer formed from a first low-K inorganic dielectric material over the substrate to cover the exposed surface of the base metal interconnect structure;

an etch-stop layer formed from a low-K organic dielectric material over the first dielectric layer;

a second dielectric layer formed from a second low-K inorganic dielectric material over the etch-stop layer;

a protective layer formed between the etch-stop layer and the second dielectric layer, wherein the material of the protective layer is difference from the material of the etch-stop layer;

a metal line formed in the second dielectric layer and the protective layer; and

metal plug connected with the metal line and penetrating through the etch-stop layer and the first dielectric layer to come into electrical contact with the base metal interconnect structure in the substrate.

2. The dual damascene structure of claim 1 , wherein the organic dielectric material used to form the etch-stop layer selected from a group consisting essentially of Flare, SILK, BCB and Parylene.

3. The dual damascene structure of claim 1 , wherein the first and second inorganic dielectric materials used to form the first and second dielectric layers are selected from a group consisting essentially of each fluorosilicate glass (FSG), fluorosilicon oxide, and hydrogen silsesquioxane.

4. The dual damascene structure of claim 1 , wherein the protective layer is formed from silicon oxide.

5. The dual damascene structure of claim 1 , wherein the protective layer is formed from silicon oxynitride.

6. The dual damascene structure of claim 1 , wherein the protective layer is formed from silicon nitride.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2020
From: INTELLECTUAL VENTURES HOLDING 81 LLC
To: INTELLECTUAL VENTURES ASSETS 158 LLC
Reel/Frame 051777/0017 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 4, 2020
From: INTELLECTUAL VENTURES ASSETS 158 LLC
To: HANGER SOLUTIONS, LLC
Reel/Frame 051486/0425 →
MERGER Recorded Jan 29, 2016
From: INTELLECTUAL VENTURES FUND 74 LLC
To: INTELLECTUAL VENTURES HOLDING 81 LLC
Reel/Frame 037625/0564 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 25, 2011
From: UNITED MICROELECTRONICS CORP.
To: INTELLECTUAL VENTURES FUND 74 LLC
Reel/Frame 026645/0414 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2011
From: YEW, TRI-RUNG; HUANG, YI-MIN; LUR, WATER; SUN, SHIH-WEI
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 026605/0102 →