IP Library Assignment 037625/0564
Patent Assignment
Reel/Frame 037625/0564

Merger

Recorded: 2016-01-29 Pages: 20
Assignor
INTELLECTUAL VENTURES FUND 74 LLC
Executed: 2015-08-27
Assignee
INTELLECTUAL VENTURES HOLDING 81 LLC
7251 W LAKE MEAD BLVD, SUITE 300, LAS VEGAS, NEVADA, 89128
Covered Properties (39)
Electrostic Discharge Protection Device Comprising a Plurality of Trenches
Patent: 5,831,312 →
Application: 08/630,024 →
Sram Having Improved Soft-Error Immunity
Patent: 5,886,375 →
Application: 08/735,007 →
Method of Manufacturing Mos Components Having Lightly Doped Drain Structures
Patent: 5,966,604 →
Application: 08/890,363 →
Dynamic Input Reference Voltage Adjuster
Patent: 5,877,615 →
Application: 08/965,581 →
Flash Eeprom Device
Patent: 5,960,285 →
Application: 08/975,490 →
Split-Gate Flash Memory Cell Structure
Patent: 5,907,172 →
Application: 08/998,312 →
Method of Manufacturing a Split-Gate Flash Memory Cell
Patent: 5,872,036 →
Application: 08/998,331 →
Method of Fabricating a Cmos Transistor
Patent: 5,904,520 →
Application: 09/002,930 →
Method of Forming Shallow Trench Isoation
Patent: 6,057,208 →
Application: 09/057,905 →
Method of Fabricating Semiconductor Devices with Self-Aligned Silicide
Patent: 6,025,241 →
Application: 09/073,576 →
Method of Forming a Dual Damascene with Dummy Metal Lines
Patent: 6,001,733 →
Application: 09/164,856 →
Flash Memory Structure and Method of Manufacture
Patent: 6,071,776 →
Application: 09/186,748 →
Method of Fabricating a Buried Contact
Patent: 6,153,498 →
Application: 09/191,247 →
Method of Automatically Forming a Rim Phase Shifting Mask
Patent: 6,291,112 →
Application: 09/191,762 →
Method of Forming Mixed Mode Devices
Patent: 6,146,960 →
Application: 09/195,744 →
Dual Damascene Structure for the Wiring-Line Structures of Multi-Level Interconnects in Integrated Circuit
Patent: 6,265,780 →
Application: 09/203,035 →
Method of Fabricating High Power Bipolar Junction Transistor
Patent: 6,140,196 →
Application: 09/203,711 →
Method of Fabricating a Dual Damascene Structure
Patent: 6,153,528 →
Application: 09/205,912 →
Method of Fabricating Dual Gate
Patent: 6,150,205 →
Application: 09/227,761 →
Method Fabricating Metal Interconnected Structure
Patent: 6,169,028 →
Application: 09/237,787 →
Method for Fabricating Metal Oxide Semiconductor
Patent: 6,190,981 →
Application: 09/243,740 →
Method for Forming Dual Damascene Structure
Patent: 6,268,283 →
Application: 09/248,159 →
Method for Manufacturing Mos Transistor
Patent: 5,972,764 →
Application: 09/270,026 →
Method of Manufacturing Flash Memory
Patent: 6,060,357 →
Application: 09/286,139 →
Method for Manufacturing Cmos
Patent: 5,981,325 →
Application: 09/299,255 →
Fabrication Method for Gate Spacer
Patent: 6,194,279 →
Application: 09/340,929 →
Method of a Metal Oxide Semiconductor on a Semconductor Wafer
Patent: 6,265,274 →
Application: 09/431,954 →
Electrostatic discharge protection circuit
Patent: 6,281,554 →
Application: 09/531,905 →
High voltage electrostatic discharge protection circuit
Patent: 6,353,247 →
Application: 09/557,513 →
Method of fabricating a mos transistor
Patent: 6,294,415 →
Application: 09/558,220 →
Method for Manufacturing a Flash Memory with Split Gate Cells
Patent: 6,436,764 →
Application: 09/590,721 →
Cassette Holder for Cleaning Equipment
Patent: 6,446,647 →
Application: 09/597,744 →
Method for Fabricating a Mos Transistor of an Embedded Memory
Patent: 6,436,759 →
Application: 09/764,330 →
Publication: US 2002/0098649
Method of Fabricating a Trenched Flash Memory Cell
Patent: 6,436,765 →
Application: 09/779,540 →
Publication: US 2002/0110984
Method of Forming Polysilicon Thin Film Transistor Structure
Patent: 6,410,373 →
Application: 09/845,438 →
Method for Fabrication of a Contact Plug in an Embedded Memory
Patent: 6,461,959 →
Application: 09/885,049 →
Polysilicon Thin Film Transistor Structure
Patent: 6,486,496 →
Application: 09/994,322 →
Publication: US 2002/0153527
Dual Damascene Structure Having Capacitors
Patent: 6,483,142 →
Application: 10/108,611 →
Publication: US 2002/0167090
Dual Damascene Structure for the Wiring-Line Structures of Multi-Level Interconnects in Integrated Circuit
Patent: 7,378,740 →
Application: 11/196,038 →
Publication: US 2005/0263876
Related Assignments (3)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Jan 4, 2020
From: INTELLECTUAL VENTURES ASSETS 158 LLC
To: HANGER SOLUTIONS, LLC
Reel/Frame 051486/0425 →
Assignment of Assignor's Interest Feb 1, 2020
From: INTELLECTUAL VENTURES HOLDING 81 LLC
To: INTELLECTUAL VENTURES ASSETS 158 LLC
Reel/Frame 051777/0017 →
Assignment of Assignor's Interest May 14, 2021
From: HANGER SOLUTIONS, LLC
To: FOOTHILLS IP LLC
Reel/Frame 056246/0533 →