Methods and apparatus for managing clock skew
View Patent ↗An apparatus is disclosed which includes a signal generator providing a first signal having a first frequency; a clock tree operative to propagate the first signal to at least one clock mesh of the apparatus; and a final buffer operative to receive the first signal, provide a second signal having a second frequency, synchronize the second signal with the first signal, and propagate the synchronized second signal to at least one other clock mesh of the apparatus.
1. Apparatus, comprising:
a signal generator providing a first signal having a first frequency;
a clock tree operative to propagate said first signal to at least one clock mesh of said apparatus; and
a final buffer operative to receive said first signal, provide a second signal having a second frequency, synchronize said second signal with said first signal, and propagate said synchronized second signal to at least one other clock mesh of said apparatus.
2. The apparatus of claim 1 wherein said final buffer is operable to divide said first frequency by a divisor to provide said second signal having said second frequency.
3. The apparatus of claim 2 wherein said clock tree is connected to said signal generator.
4. The apparatus of claim 3 wherein said at least one clock mesh is connected to said clock tree.
5. The apparatus of claim 4 wherein said at least one clock mesh comprises a plurality of clock meshes.
6. The apparatus of claim 1 wherein said final buffer comprises:
a frequency divider for receiving said first signal and providing said second signal having said second frequency; and
a synchronization circuit for synchronizing said second signal with said first signal.
7. The apparatus of claim 6 wherein said frequency divider comprises a flip flop circuit operable to receive said first signal, divide said first frequency by a divisor, and provide said second signal having said second frequency to said synchronization circuit.
8. The apparatus of claim 6 wherein said synchronization circuit comprises a digital logic circuit operable to receive said first signal and said second signal, to perform at least one logical operation on said first and second signals, and to provide as an output said synchronized second signal.
9. The apparatus of claim 8 wherein said digital logic circuit comprises at least one of: an AND gate, a NAND gate, an OR gate, and a NOR gate.
10. The apparatus of claim 1 wherein said second frequency is lower than said first frequency.
11. The apparatus of claim 6 wherein said frequency divider is operable to:
discontinue said propagation of said synchronized second signal to said at least one other clock mesh.
12. The apparatus of claim 6 wherein said synchronization circuit is operable to at least one of:
synchronize a rising edge of said second signal with a rising edge of said first signal;
synchronize a falling edge of said second signal with a falling edge of said first signal;
synchronize a rising edge of said second signal with a falling edge of said first signal; and
synchronize a falling edge of said second signal with a rising edge of said first signal.
13. A method, comprising:
providing a first signal having a first frequency;
propagating said first signal through a clock tree to at least one clock mesh of an apparatus;
generating a second signal having a second frequency;
synchronizing said second signal with said first signal; and
propagating said synchronized second signal to at least one other clock mesh of said apparatus.
14. The method of claim 13 wherein said generating said second signal comprises dividing said first frequency by a divisor.
15. The method of claim 14 wherein said divisor is about 2.
16. The method of claim 13 wherein said synchronizing comprises:
synchronizing said second signal with said first signal employing a digital logic circuit.
17. The method of claim 16 wherein said synchronizing employing said digital logic circuit comprises:
receiving said first and second signals;
performing at least one logical operation on said first and second signals; and
providing as output from said digital logic circuit said synchronized second signal.
18. The method of claim 16 wherein said digital logic circuit comprises:
at least one of: an AND gate, a NAND gate, an OR gate, and a NOR gate.
19. The method of claim 14 wherein said dividing comprises:
discontinuing said propagation of said synchronized second signal to said at least one other clock mesh.
20. The method of claim 13 wherein said synchronizing comprises at least one of:
synchronizing a rising edge of said second signal with a rising edge of said first signal;
synchronizing a falling edge of said second signal with a falling edge of said first signal;
synchronizing a rising edge of said second signal with a falling edge of said first signal; and
synchronizing a falling edge of said second signal with a rising edge of said first signal.