Method and system for switching between two (or more) reference signals for clock synchronization
View Patent ↗An apparatus and method is disclosed for synchronizing a timing signal for a computational system to different reference clock signals without impairing the operation of the computational system. A corresponding “offset” register is provided for each of the reference clock signals (RCS) for storing signal timing differences between the timing signal and RCS. When one of the reference clock signals not used for synchronizing the timing signal, is selected as the signal for synchronizing the timing signal, the corresponding offset register R 0 (for the newly selected reference clock signals) retains its last value prior to the switch, and another register R 1 stores subsequent signal timing differences between the timing signal and the newly selected reference clock signals. To synchronize the timing signal with the new reference clock signal without distorting the timing signal and impairing the operation of the computation system, differences between R 1 and R 0 are output (for successive time intervals) for iteratively adjusting the timing signals. The contents of the offset register R 0 is incrementally changed toward a predetermined value (i.e., zero) thereby gradually adjusting the timing signals to factor in a potentially large timing change when switching between reference clock signals.
1. A clock synchronization device, comprising:
a plurality of phase detectors, each phase detector receiving corresponding reference clock signals input from one of a plurality of reference clock signals;
for each of the phase detectors there are:
(a) an associated first register for receiving from the respective phase detector, a corresponding phase difference between a phase of the corresponding reference clock signals and a phase of timing signals from a computational system when the corresponding reference clock signals are used for determining the phase of the timing signals; and
(b) an associated second data register for storing data of a phase difference between the phase of the corresponding reference clock signals and the phase of the timing signals when the corresponding reference clock signals are not used for determining the phase of the timing signals;
wherein for a designated one of the reference clock signals used for determining the phase of the timing signals, the designated one of the reference clock signals is received by a first phase detector (PD 1 ) of the plurality of phase detectors, wherein PD 1 outputs to its associated first register a first value for the phase difference between the phase of the designated one of the reference clock signals and the phase of the timing signals; and
wherein for an alternative one of the reference clock signals received by a second phase detector (PD 2 ) of the plurality of the phase detectors, wherein PD 2 outputs to its associated second data register a second value of the corresponding phase difference between the phase of the alternative one of the reference clock signals and the phase of the timing signals;
circuitry for obtaining a correction in the phase of the timing signals between the phase of the designated one of the reference clock signals and the phase of the timing signals, wherein the circuitry combines:
(c) the first value, and
(d) an instance of the data from the associated second data register for PD 1 ; and
a clock selector for selecting between at least the designated one of the reference clock signals and the alternative one of the reference clock signals,
wherein, when the clock selector signals a switch from selecting the designated one of the reference signals to the alternative one of the reference clock signals, (e) and (f) following occur:
(e) PD 2 outputs, to its associated first register, a third value for a phase difference between the phase of the alternative one of the reference clock signals and the phase of the timing signals, and
(f) the circuitry combines: (i) the third value, and (ii) an instance of the data from the associated second data register for PD 2 .
2. The clock synchronization device of claim 1 , wherein at least the associated second data register for the first phase detector PD 1 is different from the associated second data register for the second phase detector PD 2 .
3. The clock synchronization device of claim 2 , wherein the associated first register for the first phase detector PD 1 is different from the associated first register for the second phase detector PD 2 .
4. The clock synchronization device of claim 1 , wherein prior to the clock selector selecting the alternative one of the reference clock signals, the circuitry combines the first value and the instance of the data from the associated second data register for PD 1 by determining a difference therebetween.
5. The clock synchronization device of claim 4 , wherein after the clock selector selects the alternative one of the reference clock signals, the circuitry combines the third value and the instance of the data from the associated second data register for PD 2 by determining a difference therebetween.
6. The clock synchronization device of claim 1 , wherein each of the first and second phase detectors PD 1 and PD 2 is included within a phase locked loop for synchronizing the timing signals with one of the designated one of the reference clock signals, and the alternative one of the reference clock signals.
7. The clock synchronization device of claim 6 , wherein at least one of the first and second phase detectors PD 1 and PD 2 receives the timing signals via a feedback connector.
8. The clock synchronization device of claim 1 , wherein, when the alternative one of the reference clock signals is selected, contents of the associated second data register for PD 2 are incrementally brought closer to zero.
9. The clock synchronization device of claim 8 , wherein the contents are modified between outputs by the associated second data register for PD 2 .
10. The clock synchronization device of claim 8 , wherein, as the content of the associated second data register for PD 2 becomes closer to zero, the system clock timing signals become more phase aligned with the alternative one of the reference clock signals.
11. The clock synchronization device of claim 1 , wherein, while the designated one of the reference clock signals is used for determining the phase of the timing signals, the associated second data register for the first phase detector PD 1 does not receive and store an update of a phase difference between the phase of the designated one of the reference clock signals and the phase of the timing signals.
12. A clock synchronization method, comprising:
receiving, by each phase detector of a plurality of phase detectors, corresponding reference clock signals input from one of a plurality of reference clock signals, each phase detector having associated first and second registers;
receiving, by the associated first register and from the respective phase detector, a corresponding phase difference between a phase of the corresponding reference clock signals and a phase of timing signals from a computational system when the corresponding reference clock signals are used for determining the phase of the timing signals;
storing, by the associated second data register, data of a phase difference between the phase of the corresponding reference clock signals and the phase of the timing signals when the corresponding reference clock signals are not used for determining the phase of the timing signals;
for a designated one of the reference clock signals used for determining the phase of the timing signals, receiving the designated one of the reference clock signals by a first phase detector (PD 1 ) of the plurality of phase detectors;
outputting, by PD 1 , to its associated first register a first value for the phase difference between the phase of the designated one of the reference clock signals and the phase of the timing signals; and
for an alternative one of the reference clock signals received by a second phase detector (PD 2 ) of the plurality of the phase detectors, outputting, by PD 2 , to its associated second data register, a second value of the corresponding phase difference between the phase of the alternative one of the reference clock signals and the phase of the timing signals;
obtaining, by circuitry, a correction in the phase of the timing signals between the phase of the designated one of the reference clock signals and the phase of the timing signals, wherein the circuitry combines:
(c) the first value, and
(d) an instance of the data from the associated second data register for PD 1 ; and
a clock selector for selecting between at least the designated one of the reference clock signals and the alternative one of the reference clock signals,
wherein, when the clock selector signals a switch from selecting the designated one of the reference clock signals to the alternative one of the reference clock signals, (e) and (f) following occur:
(e) PD 2 outputs, to its associated first register, a third value for a phase difference between the phase of the alternative one of the reference clock signals and the phase of the timing signals, and
(f) the circuitry combines: (i) the third value, and (ii) an instance of the data from the associated second data register for PD 2 .
13. The clock synchronization method of claim 12 , wherein at least the associated second data register for the first phase detector PD 1 is different from the associated second data register for the second phase detector PD 2 and wherein the associated first register for the first phase detector PD 1 is different from the associated first register for the second phase detector PD 2 .
14. The clock synchronization method of claim 12 , wherein prior to the clock selector selecting the alternative one of the reference clock signals, the circuitry combines the first value, and the instance of the data from the associated second data register for PD 1 by determining a difference therebetween and wherein after the clock selector selects the alternative one of the reference clock signals, the circuitry combines the third value, and the instance of the data from the associated second data register for PD 2 by determining a difference therebetween.
15. The clock synchronization method of claim 12 , wherein each of the first and second phase detectors PD 1 and PD 2 is included within a phase locked loop for synchronizing the timing signals with one of the designated one of the reference clock signals, and the alternative one of the reference clock signals.
16. The clock synchronization method of claim 15 , wherein at least one of the first and second phase detectors PD 1 and PD 2 receives the timing signals via a feedback connector.
17. The clock synchronization method of claim 12 , wherein, when the alternative one of the reference clock signals is selected, contents of the associated second data register for PD 2 are incrementally brought closer to zero.
18. The clock synchronization method of claim 17 , wherein the contents are modified between outputs by the associated second data register for PD 2 .
19. The clock synchronization method of claim 17 , wherein, as the contents of the associated second data register for PD 2 become closer to zero, the system clock timing signals become more phase aligned with the alternative one of the reference clock signals.
20. The clock synchronization method of claim 12 , wherein, while the designated one of the reference clock signals is used for determining the phase of the timing signals, the associated second data register for the first phase detector PD 1 does not receive and store an update of a phase difference between the phase of the designated one of the reference clock signals and the phase of the timing signals.