IP Library Granted Patent US 7,888,269
Granted Patent B2
US 7,888,269 · App. 11/256,184 · Granted Feb 15, 2011

Triple layer anti-reflective hard mask

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Quick Facts
Patent No.
US 7,888,269
App. No.
11/256,184
Granted
Feb 15, 2011
Kind
B2
Abstract

A method includes forming a layer of silicon oxynitride (SiON), silicon rich nitride (SiRN) or silicon nitride (Si 3 N 4 ) over a layer of semiconducting material. The method further includes forming a first layer of anti-reflective material over the layer of SiON, SiRN or Si 3 N 4 and forming a second layer of anti-reflective material over the first layer. The method also includes using the first layer, second layer and layer of SiON, SiRN or Si 3 N 4 as a mask when etching a pattern in the layer of semiconducting material.

Claims (31)

1. A method, comprising:

forming a first layer directly on a layer of material, the first layer being formed to a thickness ranging from about 50 Å to about 250 Å, where the first layer comprises a layer of silicon oxynitride (SiON);

forming a second layer directly on the first layer, the second layer being formed to thickness ranging from about 200 Å to about 600 Å, where the second layer comprises a layer of silicon nitride (Si 3 N 4 ) and has an extinction coefficient ranging from about 0.9 to about 1.3;

forming a third layer directly on the second layer, the third layer being formed to a thickness ranging from about 200 Å to about 400 Å, where the third layer comprises Si 3 N 4 and has an extinction coefficient ranging from about 0.2 to about 0.5; and

etching a pattern in the layer of material using the first layer, the second layer, and the third layer as a mask.

2. The method of claim 1 , further comprising:

forming a layer of photo-resist over the third layer; and

forming the pattern in the layer of photo-resist using photolithography.

3. The method of claim 1 , further comprising:

forming at least one spacer adjacent side surfaces of the first layer, the second layer, and the third layer.

4. The method of claim 1 , further comprising:

etching the first layer, the second layer, and the third layer to form a trench; and

forming a conductive bitline in the trench.

5. A method of forming a trench in a material, the method comprising:

forming a layer of silicon oxynitride (SiON) directly on the material, the layer of SiON being formed to a thickness ranging from about 50 Å to about 250 Å;

forming a first anti-reflective layer directly on the layer of SiON, the first anti-reflective layer having a first extinction coefficient ranging from about 1.0 to about 1.3 and comprising silicon nitride (Si 3 N 4 ), the first anti-reflective layer being formed to a thickness ranging from about 200 Å to about 600 Å;

forming a second anti-reflective layer directly on the first anti-reflective layer, the second anti-reflective layer having a second extinction coefficient ranging from about 0.2 to about 0.5 and comprising Si 3 N 4 , the second anti-reflective layer being formed to a thickness ranging from about 200 Å to about 400 Å;

forming a first trench through the first anti-reflective layer, the second anti-reflective layer, and the layer of SiON;

forming a second trench in the material through the first trench; and

removing the first anti-reflective layer, the second anti-reflective layer, and the layer of SiON.

6. The method of claim 5 , where forming the first trench comprises:

forming a layer of photo-resist over the second anti-reflective layer;

forming, using photolithography, a pattern in the photo-resist that corresponds to a shape of the first trench; and

etching the first anti-reflective layer, the second anti-reflective layer and the layer of SiON to create the first trench.

7. The method of claim 5 , further comprising:

filling the first trench and the second trench with an oxide material.

8. The method of claim 7 , further comprising:

polishing the first anti-reflective layer, the second anti-reflective layer, and a portion of the layer of SiON to leave a residual portion of the layer of SiON.

9. The method of claim 5 , forming at least one spacer adjacent side surfaces of the layer of SiON, the first anti-reflective layer, and the second anti-reflective layer.

10. The method of claim 5 , further comprising:

forming a conductive bitline in the second trench.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 22, 2018
From: GLOBALFOUNDRIES INC
To: SPANSION LLC
Reel/Frame 046181/0465 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
AFFIRMATION OF PATENT ASSIGNMENT Recorded Aug 18, 2009
From: ADVANCED MICRO DEVICES, INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 023120/0426 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 24, 2005
From: TOKUNO, HIROKAZU; RAEDER, CHRISTOPHER H.; FOSTER, CHRISTOPHER; QIAN, WEIDONG; NGO, MINH VAN
To: SPANSION LLC
Reel/Frame 017133/0706 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 24, 2005
From: GHANDEHARI, KOUROS; MATSUMOTO, DAVID
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 017133/0698 →