Non-volatile memory integrated circuit
View Patent ↗A nonvolatile memory integrated circuit arrayed in rows and columns is disclosed. Parallel lines of implant N-type regions are formed in a P-well of a semiconductor substrate, with lines of oxide material isolating each pair of the lines. Columns of memory cells straddle respective pairs of the implant region lines, with one line of the pair forming the source region and one line of the pair forming the drain region of each memory cell of the column. Each memory cell has a floating polysilicon storage gate. One of plural wordlines overlies each row of the memory cells. The portion of the wordline overlying each memory cells forms the control gate of the memory cell. Programming and erase operations occur by Fowler-Nordheim tunneling of electrons through a tunnel oxide layer between the floating gate and the source of the cell.
1. An integrated circuit comprising:
a semiconductor substrate including a first region of a first conductivity type;
parallel first and second trenches in the first region, the first and second trenches each having a sidewall, with the sidewall of the first trench facing the sidewall of the second trench;
a transistor comprising a source region of a second conductivity type implanted in the sidewall of the first trench, and a drain region of the second conductivity type implanted in the facing sidewall of the second trench, wherein a portion of the first region between source and the drain regions comprises a channel region of the transistor;
a gate over the channel region; and
a dielectric material filling the first and the second trenches.
2. The integrated circuit of claim 1 , further comprising a plurality of the transistors, wherein the source regions of the transistors are part of a continuous line of a dopant of the second conductivity type in the sidewall of the first trench, and the drain regions of the plural transistors are part of a continuous line of the dopant in the sidewall of the second trench.
3. The integrated circuit of claim 2 , wherein each said transistor comprises a nonvolatile memory cell.
4. The integrated circuit of claim 2 , wherein the gate comprises a floating gate overlaid by a control gate, wherein in the control gate is a subportion of a wordline that extends over dielectric material in the trench.
5. The integrated circuit of claim 1 , wherein a plurality of the transistors are formed between the facing sidewalls first and second trenches.
6. The integrated circuit of claim 5 , wherein the source regions of the plurality of transistors are respective subportions of a single implant region, and the drain regions of the plurality of transistors are respective subportions of a single implant region.
7. The integrated circuit of claim 1 , further comprising:
a tunnel oxide layer located over the source region and a source-side subportion of the channel region adjacent to the source region; and
a gate oxide layer located over the drain region and a drain-side subportion of the channel region adjacent to the drain region, wherein the gate oxide layer is thicker than the tunnel oxide layer.
8. The integrated circuit of claim 7 , wherein the gate comprises a floating gate overlaid by a control gate, wherein the floating gate is located over the tunnel oxide layer, and overlies the source-side subportion of the channel region, the source region and the dielectric material filling the first trench.
9. The integrated circuit of claim 8 , wherein the gate further comprises an oxide-nitride-oxide (ONO) layer between the floating gate and the control gate.
10. The integrated circuit of claim 8 , wherein the floating gate does not overlie the drain-side subportion of the channel region or the drain region.
11. The integrated circuit of claim 10 , wherein the control gate overlies the drain region, the drain-side subportion of the channel region, the source-side subportion of the channel region and the source region.
12. The integrated circuit of claim 1 , wherein the semiconductor substrate further comprises a second region of the second conductivity type, wherein the first region is located in the second region.