Scalable electrically eraseable and programmable memory (EEPROM) cell array
View Patent ↗A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of the NVM transistor. The drain regions of each NVM transistor in a column of the array are commonly connected to a corresponding bit line. The control gates of each NVM transistor in a row of the array are commonly connected to a corresponding word line. The source regions of each of the access transistors in the array are commonly coupled. The NVM cells are programmed and erased without having to apply the high programming voltage V PP across the gate dielectric layers of the access transistors. As a result, the NVM cells can be scaled down to sub-0.35 micron geometries.
1. A memory system comprising:
a first non-volatile memory cell having a first access transistor and a first non-volatile memory transistor, wherein the first access transistor has a drain region that is continuous with a source region of the first non-volatile memory transistor;
a second non-volatile memory cell having a second access transistor and a second non-volatile memory transistor, wherein the second access transistor has a drain region that is continuous with a source region of the second non-volatile memory transistor, wherein the first and second access transistors share a common source region, and wherein the first and second non-volatile memory cells are located in a first well region having a first conductivity type, and wherein the first well region is located in a second well region having a second conductivity type, opposite the first conductivity type, and wherein the first and second access transistors comprise control gates fabricated from a first polysilicon layer and wherein the first and second non-volatile memory transistors comprise floating gates fabricated from the first polysilicon layer; and
a first bit line connected to a drain of the first non-volatile memory transistor and a drain of the second non-volatile memory transistor.
2. The memory system of claim 1 , further comprising a first set of peripheral transistors having control gates fabricated from the first polysilicon layer.
3. The memory system of claim 2 , wherein the first set of peripheral transistors, the first and second access transistors and the first and second non-volatile memory transistors each include a gate dielectric layer having about the same thickness.
4. The memory system of claim 2 , wherein the first and second non-volatile memory transistors comprise control gates fabricated from a second polysilicon layer, the memory system further comprising a second set of peripheral transistors having control gates fabricated from the second polysilicon layer.
5. The memory system of claim 4 , wherein the second set of peripheral transistors includes:
a first subset of peripheral transistors, each having a gate dielectric layer having a first thickness; and
a second subset of peripheral transistors, each having a gate dielectric layer having a second thickness, greater than the first thickness.
6. The memory system of claim 5 , wherein the first set of peripheral transistors, the first and second access transistors and the first and second non-volatile memory transistors each include a gate dielectric layer having a third thickness, which is greater than the first thickness and less than the second thickness.