IP Library Granted Patent US 7,298,036
Granted Patent B2
US 7,298,036 · App. 11/283,340 · Granted Nov 20, 2007

Scaling of functional assignments in packages

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Quick Facts
Patent No.
US 7,298,036
App. No.
11/283,340
Granted
Nov 20, 2007
Kind
B2
Abstract

A family of package substrates adapted to receive a family of integrated circuits having different sizes and provide electrical connections between the integrated circuits and a circuit board. Each package substrate in the family includes a package substrate having a die side and a circuit board side. The package substrate has a size that is consistent for all of the package substrates in the family of package substrates. The die side has integrated circuit contacts disposed in a pattern designed to make electrical connections to a given integrated circuit in the family of integrated circuits for which the package substrate is designed, as defined by locations of contacts on the given integrated circuit. The circuit board side has circuit board contacts disposed in a pattern and with functional assignments that are consistent for all of the package substrates in the family of package substrates.

Claims (12)

1. A family of ball bond package substrates adapted to receive a family of integrated circuits having different sizes and provide electrical connections between the integrated circuits and a circuit board, where each package substrate in the family comprises:

a package substrate having a die side and a circuit board side, the package substrate having a size that is consistent for all of the package substrates in the family of package substrates,

the die side having ball bond integrated circuit contacts disposed in a pattern designed to make electrical connections to a given one of the different sizes of integrated circuit in the family of integrated circuits for which the package substrate is designed, as defined by locations of contacts on the given integrated circuit, and

the circuit board side having circuit board contacts with a same pattern and same functional assignments that are consistent for all of the package substrates in the family of package substrates.

2. A ball bond package substrate adapted to receive a family of integrated circuits having different sizes and provide electrical connections between the integrated circuits and a circuit board, where the package substrate comprises:

a die side and a circuit board side, and having a size that is sufficient to accommodate all of the different sizes in the family of integrated circuits,

the die side having ball bond integrated circuit contacts disposed in a pattern designed to make electrical connections to the different sizes of integrated circuits in the family of integrated circuits, as defined by locations of contacts on the integrated circuits, and

the circuit board side having circuit board contacts disposed in a pattern and with functional assignments that are consistent for all of the integrated circuits in the family of integrated circuits.

3. A family of ball bond package substrates adapted to receive a family of integrated circuits having different sizes and provide electrical connections between the integrated circuits and a circuit board, where each package substrate in the family comprises:

a die side and a circuit board side, and having a size that is consistent for all of the package substrates in the family of package substrates,

the die side having ball bond integrated circuit contacts disposed in a pattern designed to make electrical connections to a given one of the different sizes of integrated circuits in the family of integrated circuits for which the package substrate is designed, as defined by locations of contacts on the given integrated circuit, where integrated circuit contacts that exceed a maximum number of unique integrated circuit contacts are commonly electrically connected within the package substrate, and

the circuit board side having circuit board contacts disposed in a pattern that is consistent for all of the package substrates in the family of package substrates.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059723/0382 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0766 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
CHANGE OF NAME Recorded Jun 6, 2014
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 033102/0270 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 18, 2005
From: MILLER, LEAH M.; HALL, JEFFREY A.
To: LSI LOGIC CORPORATION
Reel/Frame 017273/0124 →