Non-volatile semiconductor memory device, electronic card using the same and electronic apparatus
View Patent ↗A non-volatile semiconductor memory device comprising a plurality of non-volatile semiconductor memory cells, an interface making data exchange with an external device to write/read data with respect to the non-volatile semiconductor memory cells, and a control circuit for controlling the non-volatile semiconductor memory cells, wherein the interface and the control circuit include a first read mode initialized via a first bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting (N+M)-byte (N is the n-th power of 2, n is positive integers) data via the interface, and a second read mode initialized via a second bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting K-byte (K is the k-th power of 2, k is positive integers) data via the interface.
1. A non-volatile semiconductor memory device comprising:
a plurality of non-volatile semiconductor memory cells;
an interface; and
a control circuit for controlling the non-volatile semiconductor memory cells,
wherein the device supports a first output mode for continuously outputting (N+M)-byte (N is the n-th power of 2, n is a positive integer) data via the interface, and a second output mode for continuously outputting K-byte (K is the k-th power of 2, k is a positive integer) data via the interface, and
wherein the first output mode is substantially transferred to output standby state after continuously outputting the data, and the second output mode is automatically transferred to a normal operation mode after continuously outputting the data.
2. The device according to claim 1 , wherein, in the first output mode, (N+M)-byte (N is the n-th power of 2, n is a positive integer, N>M) data is outputted.
3. The device according to claim 1 , wherein the plurality of non-volatile semiconductor memory cells include a ROM area configured to store system boot programs and an area except for the ROM area, and in the second read mode, K(K>N) byte data is read from the ROM area.
4. The device according to claim 1 , wherein the second output mode is booted according to a hardware reset signal supplied from an external device.
5. The device according to claim 1 , wherein the second output mode is booted based on a software reset command supplied from an external device.
6. The device according to claim 1 , wherein during the second output mode, part of the data inputted to the interface is invalidated.