Stackable power semiconductor package system
View Patent ↗The present invention provides a method of making a stackable power semiconductor package system comprising forming a lower lead frame, having an upward bent source lead and an upward bent gate lead, mounting a power semiconductor device on the lower lead frame utilizing interconnect structures and forming an upper lead frame wherein the upper lead frame is on the power semiconductor device.
1. A stackable power semiconductor package system comprising:
a lower lead frame, having an upward bent source lead and an upward bent gate lead wherein the upward bent source lead and the upward bent gate lead are electrical contacts located on a top surface and a bottom surface of the stackable power package;
a power semiconductor device mounted on the lower lead frame with interconnect structures comprises solder columns between a die metallization layer and a stress relief layer;
an upper lead frame is attached with solder is on the power semiconductor device;
the electrical contacts on the top of the stackable power semiconductor package are coplanar with the upper lead frame and the electrical contacts on the bottom of the stackable power semiconductor package are coplanar with the lower lead frame; and
a molding compound is located around the power semiconductor device, the lower lead frame and the upper lead frame wherein the electrical contacts are exposed on the top surface and the bottom surface of the stackable power semiconductor package system by the molding compound that is coplanar with the lower lead frame and the upper lead frame.
2. The system as claimed in claim 1 further comprising a stack of the stackable power semiconductor package system, wherein the stackable power semiconductor package system has complementary interfaces and individual contacts provide electrical and thermal connection to the PCB for all stacked packages.
3. The system as claimed in claim 1 further comprising a clearance in the lower lead frame for the molding compound across the bottom of the stackable power semiconductor package system.
4. The system as claimed in claim 1 wherein the molding compound is solder resist regions located around the lower lead frame and the upper lead frame.