IP Library › Assignment 052935/0327
Patent Assignment
Reel/Frame 052935/0327

RELEASE OF SECURITY INTEREST

Recorded: 2020-06-15 Received: 2020-06-15 Pages: 27
Assignor
Assignees
STATS CHIPPAC, INC.
46429 LANDING PARKWAY, FREMONT, CA, 94538, UNITED STATES
STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
5 YISHUN STREET 23, SINGAPORE, SGX, 768442, SINGAPORE
Covered Applications (100)
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED DEVICE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/488,557
→
INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM AND METHOD OF MANUFACTURE THEREOF
App. No. 12/409,491
→
OPTICAL DIE-DOWN QUAD FLAT NON-LEADED PACKAGE
App. No. 12/353,489
→
INTEGRATED CIRCUIT UNDERFILL PACKAGE SYSTEM
App. No. 12/336,141
→
SEMICONDUCTOR DEVICE AND METHOD OF PLACING SEMICONDUCTOR DIE ON A TEMPORARY CARRIER USING FIDUCIAL PATTERNS
App. No. 12/332,077
→
MULTI-CHIP PACKAGE SYSTEM INCORPORATING AN INTERNAL STACKING MODULE WITH SUPPORT PROTRUSIONS
App. No. 12/248,878
→
STACKED INTEGRATED CIRCUIT LEADFRAME PACKAGE SYSTEM
App. No. 12/236,227
→
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING STACKED DIE
App. No. 12/235,521
→
TRIPLE TIER PACKAGE ON PACKAGE SYSTEM
App. No. 12/188,210
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING ALONG A PROFILE DISPOSED IN PERIPHERAL REGION AROUND THE DEVICE
App. No. 12/140,092
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING RECESSED CONDUCTIVE VIAS IN SAW STREETS
App. No. 12/133,177
→
PACKAGE-ON-PACKAGE SYSTEM WITH HEAT SPREADER
App. No. 12/131,038
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THROUGH VIAS WITH REFLOWED CONDUCTIVE MATERIAL
App. No. 12/127,417
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING EMBEDDED PASSIVE CIRCUIT ELEMENTS INTERCONNECTED TO THROUGH HOLE VIAS
App. No. 12/127,472
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING DOUBLE-SIDED THROUGH VIAS IN SAW STREETS
App. No. 12/127,357
→
METHOD OF FABRICATING MODULE HAVING STACKED CHIP SCALE SEMICONDUCTOR PACKAGES
App. No. 12/125,770
→
INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE SYSTEM WITH CENTRAL BOND WIRES
App. No. 12/101,961
→
A METHOD OF FORMING A BUMP-ON-LEAD FLIP CHIP INTERCONNECTION HAVING HIGHER ESCAPE ROUTING DENSITY
App. No. 12/062,293
→
STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 12/056,418
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKING MODULE
App. No. 12/055,962
→
FLIP CHIP INTERCONNECTION STRUCTURE WITH BUMP ON PARTIAL PAD AND METHOD THEREOF
App. No. 12/055,152
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ISOLATED LEADS
App. No. 12/050,428
→
STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD OF MANUFACTURE THEREFOR
App. No. 12/045,606
→
METHOD OF FABRICATING A SEMICONDUCTOR MULTI PACKAGE MODULE HAVING AN INVERTED PACKAGE STACKED OVER BALL GRID ARRAY (BGA) PACKAGE
App. No. 12/042,312
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH UNDERFILL
App. No. 12/037,084
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PEDESTAL STRUCTURE
App. No. 11/968,626
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SHIELDING
App. No. 11/965,586
→
SYSTEM-IN-PACKAGE HAVING INTEGRATED PASSIVE DEVICES AND METHOD THEREFOR
App. No. 11/964,529
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE INTEGRATION
App. No. 11/958,838
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH THERMO-MECHANICAL INTERLOCKING SUBSTRATES
App. No. 11/953,340
→
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING PASSIVE CIRCUIT ELEMENTS WITH THROUGH SILICON VIAS TO BACKSIDE INTERCONNECT STRUCTURES
App. No. 11/947,617
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE SUBSTRATE HAVING CORNER CONTACTS
App. No. 11/941,409
→
ELECTROSTATIC DISCHARGE (ESD) PROTECTION STRUCTURE
App. No. 11/934,654
→
MICRO CHIP-SCALE-PACKAGE SYSTEM
App. No. 11/869,737
→
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING DIE STACKING
App. No. 11/869,738
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOLD LOCK SUBASSEMBLY
App. No. 11/865,064
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PASSIVE COMPONENTS
App. No. 11/859,462
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE DEVICE UNITS
App. No. 11/858,588
→
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
App. No. 11/858,861
→
INTEGRATED CIRCUIT PACKAGE SYSTEM FOR CHIP ON LEAD
App. No. 11/856,879
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INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE SYSTEM WITH ANTI-MOLD FLASH FEATURE
App. No. 11/850,197
→
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH CARRIER INTERPOSER
App. No. 11/849,127
→
STACKED DIE PACKAGE SYSTEM
App. No. 11/844,354
→
INTEGRATED CIRCUIT PACKAGING SYSTEM FOR FINE PITCH SUBSTRATES
App. No. 11/833,882
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH TOP AND BOTTOM TERMINALS
App. No. 11/768,730
→
GROOVING BUMPED WAFER PRE-UNDERFILL SYSTEM
App. No. 11/766,710
→
STACKED SEMICONDUCTOR PACKAGES AND METHOD THEREFOR
App. No. 11/760,712
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CONTOURED DIE
App. No. 11/759,227
→
STANDOFF HEIGHT IMPROVEMENT FOR BUMPING TECHNOLOGY USING SOLDER RESIST
App. No. 11/751,440
→
THROUGH-HOLE VIA ON SAW STREETS
App. No. 11/744,657
→
EXTENDED REDISTRIBUTION LAYERS BUMPED WAFER
App. No. 11/744,743
→
INPUT DEVICES AND THEIR USE
App. No. 11/744,102
→
INTEGRATED CIRCUIT SYSTEM WITH A DEBRIS TRAPPING SYSTEM
App. No. 11/694,933
→
MULTI-CHIP PACKAGE SYSTEM WITH MULTIPLE SUBSTRATES
App. No. 11/672,164
→
MOUNTABLE INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH ADHESIVE SPACING STRUCTURES
App. No. 11/617,413
→
SOLDER JOINT FLIP CHIP INTERCONNECTION HAVING RELIEF STRUCTURE
App. No. 11/640,534
→
STACKED INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
App. No. 11/608,829
→
INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING THIN PROFILE TECHNIQUES
App. No. 11/608,123
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INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING STRUCTURAL SUPPORT
App. No. 11/635,941
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK
App. No. 11/558,404
→
STACKED DIE SEMICONDUCTOR DEVICE HAVING CIRCUIT TAPE
App. No. 11/532,387
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ARCHED PEDESTAL
App. No. 11/463,855
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SUPPORTED STACKED DIE
App. No. 11/463,505
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QUAD FLAT PACKAGE
App. No. 11/463,072
→
INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING WAFER LEVEL CHIP SCALE PACKAGING
App. No. 11/462,545
→
STACKABLE MULTI-CHIP PACKAGE SYSTEM WITH SUPPORT STRUCTURE
App. No. 11/462,568
→
INTEGRATED CIRCUIT PACKAGE SYSTEM FOR PACKAGE STACKING AND MANUFACTURING METHOD THEREOF
App. No. 11/462,588
→
INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/462,303
→
LEADED STACKED PACKAGES HAVING INTEGRATED UPPER LEAD
App. No. 11/459,568
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OFFSET STACKED DIE
App. No. 11/459,305
→
INTEGRATED CIRCUIT LEADLESS PACKAGE SYSTEM
App. No. 11/459,320
→
INTEGRATED CIRCUIT HEAT SPREADER STACKING METHOD
App. No. 11/456,846
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STIFFENER
App. No. 11/456,544
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERCONNECT SUPPORT
App. No. 11/456,532
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METHOD OF FABRICATING AN INTEGRATED CIRCUIT WITH ETCHED RING AND DIE PADDLE
App. No. 11/428,272
→
PACKAGE-ON-PACKAGE SYSTEM
App. No. 11/424,202
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH EDGE CONNECTION SYSTEM
App. No. 11/421,051
→
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING SHIELD
App. No. 11/419,748
→
FLIP CHIP INTERCONNECTION
App. No. 11/435,305
→
OFFSET INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM
App. No. 11/383,407
→
MULTIPLE CHIP PACKAGE MODULE INCLUDING DIE STACKED OVER ENCAPSULATED PACKAGE
App. No. 11/381,901
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SEMICONDUCTOR MULTIPACKAGE MODULE INCLUDING TAPE SUBSTRATE LAND GRID ARRAY PACKAGE STACKED OVER BALL GRID ARRAY PACKAGE
App. No. 11/396,954
→
MULTICHIP PACKAGE SYSTEM
App. No. 11/278,418
→
HYBRID STACKING PACKAGE SYSTEM
App. No. 11/278,420
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH GROUND RING
App. No. 11/277,991
→
MULTIPACKAGE MODULE HAVING STACKED PACKAGES WITH ASYMMETRICALLY ARRANGED DIE AND MOLDING
App. No. 11/394,363
→
SYSTEM FOR REMOVAL OF AN INTEGRATED CIRCUIT FROM A MOUNT MATERIAL
App. No. 11/276,945
→
SEMICONDUCTOR PACKAGE SYSTEM WITH SUBSTRATE HAVING DIFFERENT BONDABLE HEIGHTS AT LEAD FINGER TIPS
App. No. 11/276,681
→
STACKABLE INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/307,906
→
SEMICONDUCTOR PACKAGE SYSTEM WITH THERMAL DIE BONDING
App. No. 11/307,614
→
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING ZERO FILLET RESIN
App. No. 11/307,482
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THERMALLY ENHANCED POWER SEMICONDUCTOR PACKAGE SYSTEM
App. No. 11/307,285
→
INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/307,313
→
STACKABLE POWER SEMICONDUCTOR PACKAGE SYSTEM
App. No. 11/307,247
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INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING HONEYCOMB MOLDING
App. No. 11/306,854
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH IMAGE SENSOR SYSTEM
App. No. 11/326,206
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DIE AND PACKAGE COMBINATION
App. No. 11/164,453
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INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING HIGH-DENSITY SMALL FOOTPRINT SYSTEM-IN-PACKAGE
App. No. 11/163,771
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADFRAME SUBSTRATE
App. No. 11/163,561
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SEMICONDUCTOR SYSTEM WITH FINE PITCH LEAD FINGERS
App. No. 11/162,617
→