Stackable integrated circuit package system
View Patent ↗A stackable integrated circuit package system is provided placing a first integrated circuit die having an interconnect provided thereon in a substrate having a cavity, encapsulating the first integrated circuit die, having the interconnect exposed, in the cavity and along a first side of the substrate, mounting a second integrated circuit die to the first integrated circuit die, and encapsulating the second integrated circuit die along a second side of the substrate.
1. A method of manufacture of a stackable integrated circuit package system comprising:
providing a substrate having a first side and a second side opposite the first side, the substrate having a cavity provided therein;
placing a first integrated circuit die in the cavity with a first interconnect extending out from the cavity without connection and a second interconnect connected to the first side;
encapsulating the first integrated circuit die, the second interconnect, and a portion of the first interconnect in a first encapsulant;
mounting a second integrated circuit die to the first integrated circuit die with a third interconnect connected to the second side;
encapsulating the second integrated circuit die and the third interconnect in a second encapsulant; and
mounting external interconnects, not encapsulated by the second encapsulant, to the second side of the substrate.
2. The method as claimed in claim 1 wherein encapsulating the first integrated circuit die comprises covering the first side.
3. The method as claimed in claim 1 wherein encapsulating the first integrated circuit die comprises forming a center gate mold on the first side.
4. The method as claimed in claim 1 wherein encapsulating the first integrated circuit die comprises:
covering the first integrated circuit die with an encapsulant; and
covering the encapsulant with the interconnect exposed.
5. The method as claimed in claim 1 wherein encapsulating the second integrated circuit die comprises encapsulating the second integrated circuit die having the interconnect provided thereon exposed.
6. A method of manufacture of a stackable integrated circuit package system comprising:
providing a substrate having a first side and a second side opposite the first side, the substrate having a cavity provided therein;
placing a first integrated circuit die in the cavity with a first interconnect extending out from the cavity without connection;
electrically connecting the first integrated circuit die and the first side with a second interconnect;
encapsulating the first integrated circuit die, the second interconnect, and a portion of the first interconnect in a first encapslant;
mounting a second integrated circuit die to the first integrated circuit die;
electrically connecting the second integrated circuit die with a third interconnect to the second side;
encapsulating the second integrated circuit die and the third interconnect in a second encapsulant; and
mounting external interconnects, not encapsulated by the second encapsulant, to the second side.
7. The method as claimed in claim 6 further comprising:
forming a top package having a top external interconnect; and
mounting the top package on the stackable integrated circuit package system with the top external interconnect attached to the interconnect.
8. The method as claimed in claim 6 further comprising:
forming a top package having a top external interconnect; and
mounting the top package on the stackable integrated circuit package system with the top external interconnect attached to the interconnect and the first side.
9. The method as claimed in claim 6 wherein encapsulating the second integrated circuit die comprises forming a center gate mold on the second side.
10. The method as claimed in claim 6 further comprising attaching a further external interconnect to the first side.