Stackable multi-chip package system with support structure

1. A method of manufacturing a stackable multi-chip package system comprising:

forming L-shape external interconnects, wherein each of the L-shape external interconnect having a base, a first land, a second land and a tip and a paddle including a first L-shape external interconnect having the base coplanar to the tip of a second L-shape external interconnect;

mounting a first integrated circuit die over the paddle;

stacking a second integrated circuit die over the paddle with the first integrated circuit die in an active side to active side configuration between the second integrated circuit die and the paddle;

connecting the first integrated circuit die and the base of the first L-shape external interconnect;

connecting the second integrated circuit die and the base of the second L-shape external interconnect; and

molding an encapsulation on the first integrated circuit die, the second integrated circuit die, the paddle, and the L-shape external interconnects with the encapsulation coplanar with the first land and the second land.

2. The method as claimed in claim 1 further comprising stacking a first stackable multi-chip package system over a second stackable multi-chip package system.

3. The method as claimed in claim 1 further comprising:

mounting a first stackable multi-chip package system over a substrate;

stacking a second stackable multi-chip package system over the first stackable multi-chip package system; and

molding the first stackable multi-chip package system and the second stackable multi-chip package system with the substrate.

4. The method as claimed in claim 1 wherein:

connecting the first integrated circuit die and the base of the first L-shape external interconnect includes connecting the first integrated circuit die and an inner portion of the base; and

connecting the second integrated circuit die and the base of the second L-shape external interconnect includes:

connecting the second integrated circuit die and an inner portion of the base; and

forming the L-shape external interconnect connected to the second integrated circuit die is in an inverted configuration to the L-shape external interconnect connected to the first integrated circuit die.

5. The method as claimed in claim 1 wherein stacking the second integrated circuit die over the first integrated circuit die in the active side to active side configuration includes facing a second active side of the second integrated circuit die to the first active side of the first integrated circuit die.

6. A method of manufacturing a stackable multi-chip package system comprising:

forming L-shape external interconnects, having a base, a first land, a second land, and a tip, and a die-attach paddle including a first external interconnect having the first land coplanar to the second land of a second external interconnect;

attaching a first integrated circuit die on the die-attach paddle with an adhesive;

stacking a second integrated circuit die over the first integrated circuit die in an offset and active side to active side configuration;

connecting the first integrated circuit die and an inner portion of the base of the first external interconnect;

connecting the second integrated circuit die and the inner portion of the base of the second external interconnect with the L-shape external interconnect connected to the second integrated circuit die in an inverted configuration to the L-shape external interconnect connected to the first integrated circuit die; and

molding an encapsulation on the first integrated circuit die with the second integrated circuit die, the die-attach paddle, and the L-shape external interconnects with the encapsulation coplanar with the first land and the second land.

7. The method as claimed in claim 6 wherein molding the first integrated circuit die with the second integrated circuit die, the die-attach paddle, and the L-shaped external interconnect partially exposed includes:

exposing a second non-active side of the second integrated circuit die; and

exposing a side of the die-attach paddle opposite the first integrated circuit die.

8. The method as claimed in claim 6 wherein forming the die-attach paddle includes forming the die-attach paddle with a conductive material having planar rigidity.

9. The method as claimed in claim 6 further comprising forming dual rows of lands with bases and tips exposed in alternating positions.

10. The method as claimed in claim 6 wherein forming the die-attach paddle includes forming an electromagnetic interference shield.