IP Library Granted Patent US 7,427,553
Granted Patent B2
US 7,427,553 · App. 11/320,910 · Granted Sep 23, 2008

Fabricating method of semiconductor device

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Quick Facts
Patent No.
US 7,427,553
App. No.
11/320,910
Granted
Sep 23, 2008
Kind
B2
Abstract

A fabricating method of a semiconductor device is provided. The method comprises the steps of preparing a semiconductor substrate having an active area with a high voltage device area and a low voltage device area and an inactive area, forming a trench in the inactive area of the semiconductor substrate, forming a sacrifice oxide layer on an inner surface of the trench, forming a liner oxide layer on the sacrifice oxide layer, forming a gap-fill oxide layer as a device isolation layer on the liner oxide layer to fill up the trench, forming a buffer oxide layer on top surfaces of the liner and sacrifice oxide layers of the device isolation layer, and forming a gate oxide layer on the high voltage device area of the semiconductor substrate to have a uniform thickness.

Claims (24)

1. A method of fabricating a semiconductor device, comprising the steps of:

preparing a semiconductor substrate having an active area with a high voltage device area and a low voltage device area and an inactive area;

forming a trench in the inactive area of the semiconductor substrate;

forming a sacrifice oxide layer on an inner surface of the trench;

forming a liner oxide layer on the sacrifice oxide layer;

forming a gap-fill oxide layer as a device isolation layer on the liner oxide layer to fill up the trench;

forming a buffer oxide layer on top surfaces of the liner and sacrifice oxide layers of the device isolation layer; and

forming a gate oxide layer on the high voltage device area of the semiconductor substrate to have a uniform thickness.

2. A method of fabricating a semiconductor device, comprising the steps of:

preparing a semiconductor substrate having an active area with a high voltage device area and a low voltage device area and an inactive area;

forming a nitride layer pattern on the semiconductor substrate to expose a portion corresponding to the inactive area;

etching the semiconductor substrate of the exposed portion using the nitride layer pattern as a mask, to form a trench in the inactive area of the semiconductor substrate;

etching a portion of the nitride layer pattern in the vicinity of an edge of the trench such that the etched portion forms an interior angle of less than 90° relative to the top surface of the device;

forming a liner oxide layer on an inner surface of the trench to have a rounded cross-section at a portion contacting with a top surface of the semiconductor substrate;

forming a gap-fill oxide layer on the liner oxide layer to fill up the; and

forming a gate oxide layer on the high voltage device area of the semiconductor substrate to have a uniform thickness.

3. A method of fabricating a semiconductor device, comprising the steps of:

preparing a semiconductor substrate having an active area with a high voltage device area and a low voltage device area and an inactive area;

forming a nitride layer pattern on the semiconductor substrate to expose a portion corresponding to the inactive area;

etching a portion of the nitride layer pattern at the inactive area such that the portion of nitride layer pattern has an interior angle less than 90° relative to the top surface of the device;

forming a trench in the exposed semiconductor substrate using the etched nitride layer pattern;

forming the device isolation layer in the trench as the etched nitride layer pattern remains on the substrate; and

forming a gate oxide layer on the high voltage device area of the semiconductor substrate to have a uniform thickness.

4. The method of claim 3 , wherein the device isolation layer is formed projecting from a top surface of the semiconductor substrate, and wherein a lateral side of the projected portion has an exterior angle greater than 90° relative the top surface of the semiconductor substrate.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2019
From: DB HITEK CO., LTD.
To: COLUMBA TECHNOLOGIES INC.
Reel/Frame 049709/0857 →
CHANGE OF NAME Recorded Nov 30, 2017
From: DONGBU HITEK CO., LTD.
To: DB HITEK CO., LTD
Reel/Frame 044555/0913 →
MERGER AND CHANGE OF NAME Recorded Nov 29, 2017
From: DONGBU ELECTRONICS CO., LTD.; DONGBU HITEK CO., LTD.
To: DONGBU HITEK CO., LTD.
Reel/Frame 044533/0523 →
CHANGE OF NAME Recorded Jun 15, 2006
From: DONGBUANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 018176/0351 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 30, 2005
From: KIM, CHANG NAM
To: DONGBUANAM SEMICONDUCTOR INC.
Reel/Frame 017426/0467 →