Method of manufacturing a semiconductor device
View Patent ↗According to an exemplary embodiment of the present invention, a method of manufacturing a semiconductor device having active regions including a SONOS device region, a high voltage device region, and a logic device region, includes defining the active regions by forming a device isolation region on a semiconductor substrate; performing ion-implantation in the SONOS device region to control a threshold voltage of a SONOS device; performing ion-implantation in the high voltage device region to form a well; performing ion-implantation in the SONOS device region and the logic device region to form a well; and forming an ONO pattern on the SONOS device region, generally by performing a photolithography and etching process on the ONO layer.
1. A method of manufacturing a semiconductor device having active regions including a SONOS device region, a high voltage device region, and a logic device region, comprising:
defining the active regions by forming device isolation regions on a semiconductor substrate;
implanting first ions in the SONOS device region to control a threshold voltage of a SONOS device;
implanting second ions in the high voltage device region to form a first well;
implanting third ions into an entire width of the SONOS device region between adjacent device isolation regions and into an entire width of the logic device region between adjacent device isolation regions to form a plurality of second wells, wherein a depth of the plurality of second wells is less than a depth of the device isolation regions; and
forming an ONO pattern on the SONOS device region.
2. The method of claim 1 , further comprising:
forming a first gate oxide layer on the high voltage device region and the SONOS device; and
forming a second gate oxide layer on the logic device region.
3. The method of claim 1 , wherein the ONO layer comprises a first oxide layer, a nitride layer, and a second oxide layer.
4. The method of claim 1 , further comprising forming a pad oxide layer over the active regions prior to implanting first, second, and third ions in the active regions.
5. The method of claim 1 , wherein the ONO pattern is formed on the SONOS device region including the second well.
6. The method of claim 1 , wherein the third ions are implanted simultaneously in the SONOS device region and in the logic device region to form the plurality of second wells.
7. The method of claim 2 , wherein forming the second gate oxide layer further comprises:
forming said first gate oxide layer on the logic device region; and
after removing the first gate oxide layer on the logic device region, forming the second gate oxide layer on the logic device region.
8. The method of claim 2 , further comprising:
forming a gate electrode on the first gate oxide layer, the second gate oxide layer, and the SONOS device region.
9. The method of claim 2 , wherein the ONO layer comprises a first oxide layer, a nitride layer, and a second oxide layer.
10. The method of claim 2 , wherein patterning the first oxide layer, the nitride layer, and the second oxide layer exposes a portion of the upper surface of the semiconductor substrate in the SONOS device region, and the portion of the upper surface of the semiconductor substrate is covered by the first gate oxide layer.
11. The method of claim 3 , wherein the plurality of second wells comprises an NMOS well region and a PMOS well region in the logic device region, the NMOS well region and the PMOS well region being separated by the device isolation regions.
12. The method of claim 4 , further comprising forming an ONO layer on the semiconductor substrate by sequentially depositing a first oxide layer, a nitride layer, and a second oxide layer prior to forming the ONO pattern.
13. The method of claim 12 , wherein patterning the first oxide layer, the nitride layer, and the second oxide layer comprises performing a photolithography and etching process.
14. The method of claim 12 , further comprising removing the pad oxide layer prior to forming the first oxide layer, the nitride layer, and the second oxide layer.
15. The method of claim 11 , wherein the plurality of second wells further comprises a second PMOS well region in the SONOS device region, the second PMOS well region being separated from the PMOS well region by the device isolation regions.
16. The method of claim 15 , wherein the first well has a depth that is less than the depth of the device isolation regions and the first well comprises a second NMOS well region and a third PMOS well region, the second NMOS well region and the third PMOS well region being separated by the device isolation regions.
17. The method of claim 16 , wherein the second NMOS well region is separated from the second PMOS well region by the device isolation regions.
18. The method of claim 17 , further comprising forming a polysilicon layer over the semiconductor device and on the second oxide layer after forming the ONO pattern, and patterning the polysilicon layer to form gate electrodes over the SONOS device region, the high voltage device region, and the logic device region.
19. The method of claim 18 , further comprising patterning the polysilicon layer to form gate electrodes over the NMOS well region in the logic device region, the PMOS well region in the logic device region, the ONO pattern in the SONOS device region, the second NMOS well region in the high voltage device region, and the third PMOS well region in the high voltage device region.
20. The method of claim 16 , wherein the second ions are implanted into entire widths of the second NMOS well region and the third PMOS well region between the device isolation regions.