IP Library Granted Patent US 8,276,185
Granted Patent B2
US 8,276,185 · App. 11/337,085 · Granted Sep 25, 2012

Enhanced security memory access method and architecture

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Quick Facts
Patent No.
US 8,276,185
App. No.
11/337,085
Granted
Sep 25, 2012
Kind
B2
Abstract

A memory device includes: at least one storage area for storing data; a protection control structure adapted to selectively allow an external device access to the at least one storage area of the memory, the storage area being not freely accessible by the external device if protected; a control logic adapted to identify an access request by the external device to the at least one storage area and cooperating with the protection control structure for managing an unlock procedure for selectively granting the external device at least temporary access rights to the storage area if protected; means for providing a first code to the external device in said unlock procedure; means for receiving a second code from the external device in response to said first code; means for verifying validity of the received second code. The means for verifying validity are adapted to ascertain a correspondence of the second code with the first code based on a predetermined relationship. The control logic instructs the protection control structure to grant access to the storage area if the validity of the received second code has been verified. The first code issued by the memory device to the external device upon receiving an access request is changed after performing predetermined number of unlock procedures.

Claims (51)

1. A method of allowing access to a memory device by an external device, the method including:

receiving at the memory device an access request to a selected storage area by the external device; and

performing an unlock procedure including:

issuing a first code to the external device, the first code issued by the memory device;

sending the first code to the external device;

receiving, from the external device, a second code at the memory device, the second code being generated by a first encryption process performed on the first code to obtain the second code;

at the memory device, temporarily unlocking the selected storage area to allow the external device to access the selected storage area more than once over a predetermined time interval based on the received second code, the temporarily unlocking including performing at least one second encryption process on the second code to obtain the first code;

relocking the storage area after lapse of the predetermined time interval;

changing the first code to a new value; and

unlocking the storage area and granting the external device access to the storage area again for the predetermined time interval in response to verifying the validity of the received second code, as changed based on the new value of the first code.

2. The method of claim 1 , in which the performing at least one second encryption process includes:

performing the at least one second encryption process on the received second code to obtain a third code; and

temporarily unlocking conditioned by a comparison of the third code to the first code.

3. The method of claim 2 , wherein the allowing the external device access to the selected storage area includes establishing an identity of the third code to the first code.

4. The method of claim 1 , in which the temporarily unlocking is conditioned by a comparison of the received second code with a fourth code, the fourth code being used by the memory device for generating the first code by performing the at least one second encryption process.

5. The method of claim 1 , in which the performing the first encryption process includes exploiting a predetermined first encryption key.

6. The method according to claim 5 , in which the performing the at least second encryption process includes exploiting a predetermined second encryption key.

7. The method according to claim 6 , in which the second encryption key is stored in the memory device.

8. An integrated circuit, comprising:

a memory location operable to store data;

a random-number generator coupled to the integrated circuit; and

a data-encryption circuit coupled to the random-number generator and to the integrated circuit, the integrated circuit operable to:

send a first code value to a requestor external to the integrated circuit in response to a first request from the requestor to access the memory location;

receive a second code value from the requestor after sending the first code value, the second code value being an encrypted version of the first code value;

compare the second code value to a predetermined code value;

allow the requestor access to the memory location more than once over a predetermined time interval if the second code value has a predetermined relationship to the predetermined code value;

change the first code value after lapse of the limited time period;

send the changed first code value to the requestor;

receive a changed second code value from the requestor;

compare the changed second code value to a predetermined code value, and

allow the requestor to access the memory location again over the predetermined time interval if the changed second code value has a predetermined relationship to the predetermined code value, the control circuit being further operable to

cause the generator to generate a random number,

cause the data-encryption circuit to encrypt the random number using a predetermined encryption key, and

send to the requestor the encrypted random number as the first code value.

9. The integrated circuit of claim 8 , further comprising:

a random-number generator coupled to the control circuit;

a data-encryption circuit coupled to the random-number generator and to the control circuit;

the control circuit being is further operable to

cause the generator to generate a random number,

cause the data-encryption circuit to encrypt the random number using a predetermined encryption key, and

send to the requester the encrypted random number as the first code value.

10. A computer-readable storage device containing instructions that, when executed by a processor, causes the processor to perform a method of allowing access to a memory device by an external device, the method comprising:

receiving at the memory device an access request to a selected storage area by the external device; and

performing an unlock procedure including:

issuing a first code to the external device, the first code issued by the memory device;

sending the first code to the external device;

receiving, from the external device, a second code at the memory device, the second code being generated by a first encryption process performed on the first code to obtain the second code;

at the memory device, temporarily unlocking the selected storage area to allow the external device to access the selected storage area more than once over a predetermined time interval based on the received second code, the temporarily unlocking including performing at least one second encryption process on the second code to obtain the first code;

relocking the storage area after lapse of the predetermined time interval;

changing the first code to a new value; and

unlocking the storage area and granting the external device access to the storage area again for the predetermined time interval in response to verifying the validity of the received second code, as changed based on the new value of the first code.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
CORRECTIVE RECORDATION COVERSHEET AND APPENDIX TO REMOVE ERRONEOUSLY LISTED APPLICATION SERIAL NO. 11/495876 ON REEL 029406 FRAME 001 Recorded Dec 11, 2013
From: NUMONYX B.V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032069/0337 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2013
From: STMICROELECTRONICS S.R.L.
To: STMICROELECTRONICS NV
Reel/Frame 029631/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2012
From: NUMONYX B.V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 029406/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 4, 2012
From: STMICROELECTRONICS N.V.
To: NUMONYX B.V.
Reel/Frame 029076/0493 →