Memory device with a ramp-like voltage biasing structure based on a current generator
View Patent ↗A memory device includes a plurality of memory cells each one for storing a value, at least one reference cell, biasing means for biasing a set of selected memory cells and the at least one reference cell with a biasing voltage having a substantially monotone time pattern, means for detecting the reaching of a threshold value by a current of each selected memory cell and of each reference cell, and means for determining the value stored in each selected memory cell according to a temporal relation of the reaching of the threshold value by the currents of the selected memory cell and of the at least one reference cell. The biasing means includes means for applying a controlled biasing current to the selected memory cells and to the at least one reference cell.
1. A memory device, comprising:
a plurality of memory cells each one for storing a value;
a reference cell;
biasing means for biasing a set of selected memory cells of the plurality of memory cells and the reference cell with a biasing voltage having a substantially monotone time pattern;
means for detecting reaching of a threshold value by respective currents of the selected memory cells and of the reference cell; and
means for determining the value stored in each selected memory cell according to a temporal relation of the reaching of the threshold value by the currents of the selected memory cell and of the reference cell, wherein:
the biasing means includes means for applying a controlled biasing current to the selected memory cells and to the reference cell.
2. The memory device according to claim 1 , wherein the biasing current is a constant current, the biasing voltage including a ramp-like portion with a constant slope.
3. The memory device according to claim 1 , wherein the biasing means includes means for applying the biasing current to a common node from which a first path and a second path branch, the first path including the selected memory cells and the second path including the reference cell.
4. The memory device according to claim 3 , further including means for equalizing an equivalent resistance of the first path with an equivalent resistance of the second path.
5. The memory device according to claim 3 , further including means for equalizing an equivalent capacitance of the first path with an equivalent capacitance of the second path.
6. The memory device according to claim 1 , further including means for trimming the biasing current.
7. The memory device according to claim 6 , wherein the means for trimming includes a plurality of trimming elements each one for providing a correction current of the biasing current and means for selectively enabling each trimming element, the correction currents having at least two different absolute values.
8. The memory device according to claim 1 , wherein the memory device is non-volatile.
9. The memory device according to claim 8 , wherein the memory device is a multi-level memory device.
10. A method for reading a memory device including a plurality of memory cells, each one for storing a value, and a reference cell, the method comprising the steps of:
biasing a set of selected memory cells of the plurality of memory cells and the reference cell with a biasing voltage having a substantially monotone time pattern;
detecting the reaching of a threshold value by respective currents of the selected memory cells and of the reference cell; and
determining the value stored in each selected memory cell according to a temporal relation of the reaching of the threshold value by the currents of the selected memory cell and of the reference cell, wherein:
the step of biasing includes applying a controlled biasing current to the selected memory cells and to the reference cell.
11. The method of claim 10 , wherein the biasing current is a constant current, the biasing voltage including a ramp-like portion with a constant slope.
12. The method of claim 10 , wherein the biasing step includes applying the biasing current to a common node from which a first path and a second path branch, the first path including the selected memory cells and the second path including the reference cell.
13. The method of claim 12 , further including equalizing an equivalent resistance of the first path with an equivalent resistance of the second path.
14. The method of claim 12 , further including equalizing an equivalent capacitance of the first path with an equivalent capacitance of the second path.
15. The method of claim 10 , further including trimming the biasing current.
16. The method of claim 15 , wherein the trimming step includes selectively enabling one or more of a plurality of trimming elements, each one for providing a correction current of the biasing current, the correction currents having at least two different absolute values.
17. The method of claim 10 wherein the reference cell is one of a plurality of reference cells and the determining step includes determining the value stored in each selected memory cell according to a temporal relation of the reaching of the threshold value by the currents of the selected memory cell and of the plurality of reference cells.
18. A memory device, comprising:
a plurality of memory cells each one for storing a value;
a reference cell;
a read circuit structured to determine a value stored in a selected memory cell of the plurality of memory cells according to a temporal relation at which a threshold value is reached by currents of the selected memory cell and of the reference cell; and
a biasing circuit structured to apply a controlled biasing current to a common node from which a first path and a second path branch, the first path including the selected memory cell and the second path including the reference cell, the biasing current effecting a biasing voltage having a substantially monotone time pattern.
19. The memory device of claim 18 , wherein the biasing current is a constant current.
20. The memory device of claim 18 , further comprising a resistance coupled to the reference cell and structured to equalize an equivalent resistance of the first path with an equivalent resistance of the second path.
21. The memory device of claim 18 , further comprising a capacitance coupled to the reference cell and structured to equalize an equivalent capacitance of the first path with an equivalent capacitance of the second path.
22. The memory device of claim 18 , further comprising:
a plurality of trimming elements that provide a plurality of correction currents, respectively, the correction currents having at least two different absolute values; and
a plurality of selection switches that selectively couple the trimming elements, respectively, to the biasing current.
23. The memory device of claim 18 , wherein the memory device is non-volatile.
24. The memory device of claim 18 , wherein the memory device is a multi-level memory device.