IP Library Granted Patent US 7,736,988
Granted Patent B2
US 7,736,988 · App. 11/345,495 · Granted Jun 15, 2010

Forming structures that include a relaxed or pseudo-relaxed layer on a substrate

Assignee: S.O.I.Tec Silicon on Insulator Technologies
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,736,988
App. No.
11/345,495
Granted
Jun 15, 2010
Kind
B2
Abstract

A method for forming a relaxed or pseudo-relaxed useful layer on a substrate is described. The method includes growing a strained semiconductor layer on a donor substrate, bonding a receiver substrate to the strained semiconductor layer by a vitreous layer of a material that becomes viscous above a certain viscosity temperature to form a first structure. The method further includes detaching the donor substrate from the first structure to form a second structure comprising the receiver substrate, the vitreous layer, and the strained layer, and then heat treating the second structure at a temperature and time sufficient to relax strains in the strained semiconductor layer and to form a relaxed or pseudo-relaxed useful layer on the receiver substrate.

Claims (10)

1. A method of forming a semiconductor structure that includes a strained layer on a substrate which comprises: providing a strained semiconductor layer on a donor substrate; providing a thin, protective layer of semiconductor material on the strained layer; providing a receiving substrate; providing a glassy layer on the receiving substrate prior to bonding the donor substrate to the receiving substrate; bonding the donor substrate to the receiving substrate; transferring part of the donor substrate in the form of a layer to the receiving substrate to form a first structure that includes the transferred layer, the strained semiconductor layer, the protective layer and the receiving substrate; and transforming the transferred layer of the first structure to a further glassy layer by a heat treatment which also converts the strained semiconductor layer to a layer of relaxed or pseudo-relaxed semiconductor material and the protective layer to a layer of strained material.

2. The method of claim 1 , wherein the protective layer has a thickness of between about 100 Å and about 300 Å and is provided by epitaxially growth of the semiconductor material on the strained semiconductor layer.

3. The method of claim 1 , which further comprises removing the further glassy layer to expose the relaxed or pseudo-relaxed semiconductor layer.

4. The method of claim 3 , which further comprises providing a layer of a strained semiconductor material on the exposed relaxed or pseudo-relaxed semiconductor layer.

5. The method of claim 3 , wherein the relaxed or pseudo-relaxed layer is a SiGe layer, the protective layer is made of silicon, and which further comprises selectively etching and removing the SiGe layer to expose the strained silicon layer.

6. The method of claim 1 , wherein the donor wafer includes a zone of weakness that defines the layer to be transferred so that the donor substrate can be detached along the zone of weakness, wherein the donor substrate is fabricated by forming a porous layer on a crystalline carrier substrate and growing a crystalline layer on the porous layer, such that the porous layer comprises the zone of weakness of the donor substrate, and further wherein the donor substrate is detached along the zone of weakness by at least one of chemical etching or mechano-chemical etching.

7. The method of claim 1 , wherein the donor wafer includes a zone of weakness that defines the layer to be transferred so that the donor substrate can be detached along the zone of weakness, and wherein the zone of weakness is formed by implanting atomic species in the donor substrate and the donor substrate is detached along the zone of weakness by applying thermal or mechanical energy.

8. The method of claim 1 , which further comprises applying a bonding layer of material onto at least one of the protective layer or the receiving substrate prior to bonding the protective layer and the receiving substrate.

9. The method of claim 1 , wherein the first structure that is prepared is a Si/SiGeOI structure that includes a stressed Si layer, a relaxed SiGe layer, a SiO 2 glassy layer and the receiving substrate.

10. The method of claim 1 , which further comprises providing electrical components in the strained semiconductor layer.

Assignments (2)
CHANGE OF NAME Recorded Mar 1, 2012
From: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
To: SOITEC
Reel/Frame 027793/0535 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 28, 2012
From: GHYSELEN, BRUNO; MAZURE, CARLOS; ARENE, EMMANUEL
To: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
Reel/Frame 027772/0620 →
Priority Claims (1)
FR 03 02518 · Feb 28, 2003 · national
Continuity (3)
Continuation 1078401600 · Feb 20, 2004
Provisional Application 6048347600 · Jun 26, 2003
Related Publication 20060128117A1 · Jun 15, 2006