Granted Patent B1

US 7,245,536 · App. 11/355,394 · Granted Jul 17, 2007

Abstract

Claims (40)

1. A method of providing a reference voltage in an integrated circuit, comprising:

coupling a first set of one or more capacitors between a floating gate of a reference non-volatile memory (NVM) transistor and a reference voltage source;

coupling a second set of one or more capacitors between the floating gate and a control gate of the reference NVM transistor;

programming a threshold voltage of a first non-volatile memory (NVM) transistor while coupled in parallel with the reference NVM transistor; and

generating a single-ended reference voltage in response to the programmed threshold voltage of the first NVM transistor.

2. The method of claim 1 , further comprising transferring one or more capacitors between the first set and the second set, thereby adjusting the single-ended reference voltage.

3. The method of claim 2 , wherein the step of transferring is performed in response to one or more values stored in one or more corresponding latches.

4. The method of claim 1 , further comprising coupling each of the one or more capacitors in the first set in parallel.

5. The method of claim 1 , further comprising coupling each of the one or more capacitors in the second set in parallel.

6. The method of claim 1 , wherein the step of programming the threshold voltage of the first NVM transistor comprises:

applying a first voltage to a control gate of the first NVM transistor and the control gate of the reference NVM transistor; and

applying a programming voltage to a programming terminal of the first NVM transistor.

7. The method of claim 6 , wherein the step of programming the threshold voltage of the first NVM transistor further comprises:

removing the first programming voltage from the programming terminal of the first NVM transistor when a current through the first NVM transistor at least equals a current through the reference NVM transistor.

8. The method of claim 6 , further comprising selecting the first voltage to be ground.

9. The method of claim 2 , wherein the step of generating the single-ended reference voltage comprises:

coupling the first and reference NVM transistors in parallel in a current mirror configuration;

coupling the first and reference NVM transistors to inputs of a differential amplifier; and

coupling an output of the differential amplifier to the first set of one or more capacitors, wherein the first set of one or more capacitors is decoupled from the reference voltage source during the step of generating the single-ended reference voltage.

10. The method of claim 9 , wherein the single-ended reference voltage is provided at the output of the differential amplifier.

11. The method of claim 9 , further comprising transferring one or more capacitors between the first set and the second set, thereby adjusting the single-ended reference voltage.

12. The method of claim 1 , further comprising erasing the first NVM transistor prior to programming the threshold voltage of the first NVM transistor.

13. The method of claim 1 , wherein the threshold voltage of the first NVM transistor is programmed by Fowler-Nordheim tunneling.

14. The method of claim 1 , further comprising initializing the threshold voltage of the reference NVM transistor to a neutral state prior to programming the threshold voltage of the first NVM transistor.

15. The method of claim 14 , wherein the step of initializing the threshold voltage of the reference NVM transistor comprises exposing the reference NVM transistor to ultra-violet (UV) radiation.

16. A voltage reference circuit comprising:

a first non-volatile memory (NVM) transistor having a first control gate and a first floating gate;

a first capacitor coupled between the first control gate and the first floating gate;

a reference NVM transistor having a second control gate and a second floating gate;

a first set of one or more capacitors coupled between the second floating gate and a control terminal;

a second set of one or more capacitors coupled between the second control gate and the second floating gate; and

a control circuit configured to transfer one or more capacitors between the first and second sets of one or more capacitors.

17. The voltage reference circuit of claim 16 , wherein the first capacitor has a capacitance equal to the sum of the capacitances of the first and second sets of one or more capacitors.

18. The voltage reference circuit of claim 16 , wherein the first set of one or more capacitors comprises a first reference capacitor which is always coupled between the second floating gate and the control terminal, and the second set of one or more capacitors comprises a second reference capacitor which is always coupled between the second control gate and the second floating gate.

19. The voltage reference circuit of claim 18 , wherein the first set of one or more capacitors further comprises a plurality of adjustment capacitors, each having a first terminal coupled to the second floating gate and a second terminal coupled to an output terminal of a corresponding inverter.

20. The voltage reference circuit of claim 18 , wherein each corresponding inverter has an input terminal coupled to receive a latched control signal, wherein each latched control signal determines whether the corresponding adjustment capacitor is included in the first or second set of one or more capacitors.

21. The voltage reference circuit of claim 18 , wherein each corresponding inverter has a first power terminal coupled to the control terminal, and a second power terminal coupled to ground.

22. The voltage reference circuit of claim 19 , wherein the adjustment capacitors have capacitances that exhibit a binary weighting.

23. The voltage reference circuit of claim 16 , further comprising a differential amplifier having inputs coupled to the first and reference NVM transistors.

24. The voltage reference circuit of claim 16 , wherein the first and reference NVM transistors are connected in a current mirror configuration.

Assignments (7)