Radiation hardened logic circuit
View Patent ↗A radiation-hardened logic circuit prevents SET-induced transient pulses from propagating through the circuit, using two identical logic paths. The outputs of the two logic paths are fed into an exclusive-OR gate, which controls gating circuitry. The gating circuitry can be a controlled pass-gate circuit and a data latch, an adjustable threshold comparator, or two controlled latches. Transient pulse suppression is achieved with less circuitry and expense than is found in TMR circuits.
1. A radiation-hardened logic circuit comprising:
an exclusive-OR gate having a first input for receiving a first logic signal, a second input for receiving a second logic signal, and an output; and
gating circuitry having a first input for receiving the first logic signal, a second input for receiving the second logic signal, a control input coupled to the output of the exclusive-OR gate, a comparator having an adjustable input switching threshold controlled by the control input, and an output for providing an output logic signal.
2. The radiation-hardened logic circuit of claim 1 wherein the logic output signal is substantially similar to the first logic signal, but wherein any radiation-induced pulses are substantially attenuated or removed.
3. The radiation-hardened logic circuit of claim 1 wherein the logic output signal is substantially similar to the second logic signal, but wherein any radiation-induced pulses are substantially attenuated or removed.
4. The radiation-hardened logic circuit of claim 1 wherein the gating circuitry comprises:
a first latch having an input for receiving the first logic signal, a control input coupled to the output of the exclusive-OR gate, and an output;
a second latch having an input for receiving the second logic signal, a control input coupled to the output of the exclusive-OR gate, and an output; and
a logic gate having a first input coupled to the output of the first latch, a second input coupled to the output of the second latch, and an output for providing the output logic signal.
5. The radiation-hardened logic circuit of claim 4 wherein the logic gate comprises a two-input AND gate.
6. The radiation-hardened logic circuit of claim 1 further comprising:
a first logic block having an input for receiving an original logic signal and an output for providing the first logic signal; and
a second logic block having an input for receiving the original logic signal and an output for providing the second logic signal,
wherein the first and second logic blocks are substantially similar, and the first and second logic signals are substantially similar, except for the presence of any radiation-induced pulses.
7. A radiation-hardened logic circuit comprising:
a first input for receiving a first logic signal;
a second input for receiving a second logic signal substantially similar to the first logic signal except for the presence of radiation-induced pulses;
an output for providing a logic output signal substantially similar to either the first or the second logic signal, but wherein any radiation-induced pulses are substantially attenuated or removed;
a P-channel circuit portion having a signal input, a control input, and a signal output;
an N-channel circuit portion having a signal input, a control input, and a signal output; and
logic circuitry for receiving the first and second logic signals coupled to the signal inputs and control inputs of the P-channel and N-channel circuit portions, the signal outputs of the P-channel and N-channel circuit portions being coupled together to provide the logic output signal, and wherein the P-channel circuit portion includes
a first P-channel transistor having a gate coupled to the signal input, a drain, and a source coupled to a source of supply voltage;
a second P-channel transistor having a gate coupled to the signal input, a drain coupled to the signal output, and a source coupled to the drain of the first P-channel transistor;
a third P-channel transistor having a gate coupled to the signal output and a current path coupled between the source of the second P-channel transistor and ground;
a fourth P-channel transistor having a gate coupled to the signal output, a source, and a drain coupled to ground; and
a fifth P-channel transistor having a gate coupled to the control input, a source coupled to the drain of the first P-channel transistor, and a drain coupled to the source of the fourth P-channel transistor.
8. The radiation-hardened logic circuit of claim 7 wherein the N-channel circuit portion comprises:
a first N-channel transistor having a gate coupled to the signal input, a drain, and a source coupled to ground;
a second N-channel transistor having a gate coupled to the signal input, a drain coupled to the signal output, and a source coupled to the drain of the first N-channel transistor;
a third N-channel transistor having a gate coupled to the signal output and a current path coupled between the source of the second N-channel transistor and ground;
a fourth N-channel transistor having a gate coupled to the signal output, a source, and a drain coupled to a source of supply voltage; and
a fifth N-channel transistor having a gate coupled to the control input, a source coupled to the drain of the first N-channel transistor, and a drain coupled to the source of the fourth N-channel transistor.
9. The radiation-hardened logic circuit of claim 7 wherein the logic circuitry comprises:
a first logic gate for receiving the first and second logic signals coupled to the signal inputs of the P-channel and N-channel circuit portions; and
a second logic gate for receiving the first and second logic signals coupled to the control inputs of the P-channel and N-channel circuit portions.
10. The radiation-hardened logic circuit of claim 9 wherein the first logic gate comprises a NAND gate.
11. The radiation-hardened logic circuit of claim 9 wherein the second logic gate comprises an exclusive-OR gate.
12. A radiation-hardened logic circuit comprising:
a first input for receiving a first logic signal;
a second input for receiving a second logic signal substantially similar to the first logic signal except for the presence of radiation-induced pulses;
an output for providing a logic output signal substantially similar to either the first or the second logic signal, but wherein any radiation-induced pulses are substantially attenuated or removed;
a first inverter having an input and an output;
a second inverter having an input coupled to the output of the first inverter and an output;
a pass-gate circuit including parallel-connected N-channel and P-channel transistors having an input and an output for providing the logic output signal, and having control inputs coupled to the outputs of the first and second inverters; and
logic circuitry for receiving the first and second logic signals coupled to the inputs of the first inverter and the pass-gate circuit.
13. The radiation-hardened logic circuit of claim 12 wherein the logic circuitry comprises:
a first logic gate for receiving the first and second logic signals coupled to the input of the pass-gate circuit; and
a second logic gate for receiving the first and second logic signals coupled to the input of the first inverter.
14. The radiation-hardened logic circuit of claim 13 wherein the first logic gate comprises a NAND gate.
15. The radiation-hardened logic circuit of claim 13 wherein the second logic gate comprises an exclusive-OR gate.
16. A radiation-hardened logic circuit comprising:
an exclusive-OR gate having a first input for receiving a first logic signal, a second input for receiving a second logic signal, and an output;
gating circuitry having a first input for receiving the first logic signal, a second input for receiving the second logic signal, a control input coupled to the output of the exclusive-OR gate, a logic gate coupled to a controlled pass-gate, and an output for providing an output logic signal, wherein the logic gate comprises a two-input AND gate.
17. A radiation-hardened logic circuit comprising:
an exclusive-OR gate having a first input for receiving a first logic signal, a second input for receiving a second logic signal, and an output;
gating circuitry having a first input for receiving the first logic signal, a second input for receiving the second logic signal, a control input coupled to the output of the exclusive-OR gate, a logic gate coupled to a controlled pass-gate, and an output for providing an output logic signal; and
a latch coupled to the controlled pass-gate.