Plural output switching regulator with phase comparison and delay means
View Patent ↗Disclosed are a control circuit and control method for a comparator-controlled type DC-DC converter that can prevent the generation of audible noise due to the difference between relevant switching frequencies and prevent the increase in the input power source ripple voltage. A phase comparator FC outputs a compared-result signal CONT in correspondence with the phase difference between an output signal FP 2 and a delay signal FR 1 . A delay circuit DLY 2 performs a feedback control for adjusting the amount of retardation time in correspondence with the compared-result signal CONT. And, the delay circuit DLY 2 outputs a delay signal FR 2 after the passage of a prescribed amount of retardation time from the time when the falling edge of an output signal SQB 2 has been input. At a time t 16 that is after the passage of a prescribed amount of time, there is obtained a time delay DT 2 b that causes the period TT 1 of the delay signal FR 1 and the period TT 2 b of the output signal FP 2 to coincide with each other and that makes zero the phase difference between the delay signal FR 1 and the output signal FP 2.
1. A DC-DC converter control circuit comprising:
a first comparator that compares an output voltage and a first reference voltage and that detects a case where the output voltage crosses the first reference voltage to output a detection signal;
a flip-flop that controls a main switching transistor and that according to the output signal transits from a first state to a second state;
a phase comparator that detects the phase difference between a phase reference signal input from outside and the detection signal and outputs a phase difference signal corresponding to the phase difference; and,
a delay circuit that is connected between an output and input of the flip-flop circuit and to which there is input the phase difference signal,
whereby the delay circuit, in a case where the phase of the detection signal is more advanced than the phase of the phase reference signal, after having imparted an amount of retardation time that has been increased correspondingly to the amount of phase advanced to a transition signal input from the flip-flop at the time of the flip-flop's transiting from the first state to the second state, outputs the transition signal to which the amount of the retardation time is imparted, to the flip-flop; and the delay circuit, in a case where the phase of the detection signal is more retarded than the phase of the phase reference signal, after having imparted the amount of retardation time decreased correspondingly to the amount of phase retarded to the transition signal, outputs the transition signal to which the amount of the retardation time is imparted, to the flip-flop,
whereby the flip-flop, correspondingly to that the transition signal to which the amount of retardation time has been imparted is input, transits from the second state to the first state.
2. A DC-DC converter control circuit according to claim 1 , wherein
the phase reference signal is a signal that causes a main switching transistor equipped to another DC-DC converter to transit to a non-conductive state, whereby
when the flip-flop is in the first state, the main switching transistor is made non-conductive, whereas
when the flip-flop is in the second state, the main switching transistor is made conductive.
3. A DC-DC converter control circuit according to claim 1 , wherein
the phase reference signal is a signal that causes a main switching transistor equipped to another DC-DC converter to transit to a conductive state, whereby
when the flip-flop is in the first state, the main switching transistor is made conductive, whereas
when the flip-flop is in the second state, the main switching transistor is made non-conductive.
4. A DC-DC converter control circuit according to claim 1 , wherein it comprises, as the phase reference signal, an oscillator that outputs a clock signal.
5. A DC-DC converter control circuit according to claim 1 , wherein
the phase comparator comprises
an integrator;
a first switch that connects the integrator and a first voltage; and
a second switch that connects the integrator and a second voltage,
whereby
when the phase of the detection signal is more advanced than the phase of the phase reference signal, the circuit brings the first switch to a conductive state in correspondence with the phase difference, whereas
when the phase of the comparison frequency signal is more retarded than the phase of the reference frequency signal, the circuit brings the second switch to a conductive state in correspondence with the phase difference.
6. A DC-DC converter control circuit according to claim 1 , wherein
the delay circuit comprises
an electric current source that causes a change in the amount of current in correspondence with the phase difference signal;
a capacitor that is connected in series to the current source and one end of which is grounded;
a third switch that, corresponding to that the flip-flop is made to transit from the first state to the second state, is made conductive and that, corresponding to that the flip-flop is made to transit from the second state to the first state, is made non-conductive, and that is connected in parallel to the capacitor; and
a second comparator that outputs to the flip-flop the compared result obtained by comparing the voltage of the capacitor and a second reference voltage.
7. A DC-DC converter control method comprising:
a step that compares an output voltage and a first reference voltage and that detects a case where the output voltage crosses the first reference voltage to output a detection signal;
a step that, in correspondence with the detection signal, causes a main switching transistor to transit from a first state to a second state; and
a step of, in a case where the phase of the detection signal is more advanced than the phase of a phase reference signal, when an amount of retardation time that has been increased correspondingly to the amount of phase advanced from a time when the main switching transistor transits from the first state to the second state has lapsed, causing the main switching transistor to transit from the second state to the first state, whereas, in a case where the phase of the detection signal is more retarded than the phase of the phase reference signal, when the amount of retardation time that has been decreased correspondingly to the amount of phase advanced from a time when the main switching transistor transits from the first state to the second state has lapsed, causing the main switching transistor to transit from the second state to the first state.