Flip chip interconnection pad layout
View Patent ↗A flip chip interconnect pad layout has the die signal pads are arranged on the die surface near the perimeter of the die, and the die power and ground pads arranged on the die surface inboard from the signal pads; and has the signal pads on the corresponding package substrate arranged in a manner complementary to the die pad layout and the signal lines routed from the signal pads beneath the die edge away from the die footprint, and has the power and ground lines routed to vias beneath the die footprint. Also, a flip chip semiconductor package in which the flip chip interconnect pad layouts have the die signal pads situated in the marginal part of the die and the die power and ground pads arranged on the die surface inboard from the signal pads, and the corresponding package substrates have signal pads arranged in a manner complementary to the die pad layout and signal lines routed from the signal pads beneath the die edge away from the die footprint.
1. A substrate for flip chip mount, comprising a die attach region including a die footprint, having signal pads disposed primarily in a perimeter region of the die footprint, and having signal escape lines running in an upper metal layer outwardly and away from the die footprint, and having power and ground pads disposed primarily in an inboard region inward from the signal pads and ground and power lines dropping through vias to lower metal layers, wherein fewer than 10% of the power and ground pads are located within the perimeter region.
2. The substrate of claim 1 , wherein fewer than 5% of the power and ground pads are located within the perimeter region.
3. The substrate of claim 1 , wherein fewer than 2% of the power and ground pads are located within the perimeter region.
4. A substrate for flip chip mount, comprising a die attach region including a die footprint, having signal pads disposed primarily in a perimeter region of the die footprint, and having signal escape lines running in an upper metal layer outwardly and away from the die footprint, and having power and ground pads disposed primarily in an inboard region inward from the signal pads and ground and power lines dropping through vias to lower metal layers, wherein fewer than 10% of the signal pads are located within the inboard region.
5. The substrate of claim 4 , wherein fewer than 5% of the signal pads are located within the inboard region.
6. The substrate of claim 4 , wherein fewer than 2% of the signal pads are located within the inboard region.
7. The substrate of claim 1 , comprising a core laminate substrate.
8. The substrate of claim 4 , comprising a core laminate substrate.
9. The substrate of claim 1 , comprising a build-up substrate.
10. The substrate of claim 4 , comprising a build-up substrate.
11. The substrate of claim 1 , wherein the signal pads are arranged in two or more rows generally parallel to an edge of the die footprint, wherein the signal pads in adjacent rows are in a staggered configuration.
12. The substrate of claim 1 , wherein fewer than 10% of the signal pads are located within the inboard region.
13. The substrate of claim 1 , wherein fewer than 5% of the signal pads are located within the inboard region.
14. The substrate of claim 1 , wherein fewer than 2% of the signal pads are located within the inboard region.
15. The substrate of claim 1 , wherein the perimeter region is devoid of power and ground pads.
16. The substrate of claim 4 , wherein the power and ground pads are arranged in two or more rows generally parallel to an edge of the die footprint, wherein the power and ground pads in adjacent rows are in a staggered configuration.
17. The substrate of claim 4 , wherein fewer than 10% of the power and ground pads are located within the perimeter region.
18. The substrate of claim 4 , wherein fewer than 5% of the power and ground pads are located within the perimeter region.
19. The substrate of claim 4 , wherein fewer than 2% of the power and ground pads are located within the perimeter region.
20. The substrate of claim 4 , wherein the inboard region is devoid of signal pads.