IP Library Patent Application 11379018
Patent Application
App. No. 11/379,018

MULTICHIP PACKAGE SYSTEM

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Quick Facts
Patent No.
US None
App. No.
11/379,018
Abstract

A multichip package system is provided forming a first substrate having a first side, a second side, and a first opening, connecting a first integrated circuit die to the first substrate through the first opening, connecting a second integrated circuit die on the first substrate, and encapsulating the first integrated die and second integrated circuit die on the first substrate.

Claims (100)

1 . A multichip package system comprising:

forming a first substrate having a first side, a second side, and a first opening;

connecting a first integrated circuit die to the first substrate through the first opening;

connecting a second integrated circuit die on the first substrate; and

encapsulating the first integrated die and second integrated circuit die on the first substrate.

2 . The system as claimed in claim 1 wherein:

connecting the first integrated circuit die to the first substrate through the first opening comprises:

attaching an active side of the first integrated circuit die on the first side, and

connecting an interconnect between the active side and the second side;

connecting the second integrated circuit die further comprises:

mounting the second integrated circuit die on the second side at one side of the first opening; and

further comprising:

mounting a third integrated circuit die on the second side at an opposite side of the first opening; and

encapsulating the interconnect.

3 . The system as claimed in claim 1 further comprising:

forming the first substrate with a second opening;

attaching a first active side of the first integrated circuit die on the first side;

connecting a first interconnect between the first active side and the second side;

attaching a second active side of the second integrated circuit die on the first side;

connecting a second interconnect between the second active side and the second side through the second opening; and

encapsulating the first interconnect and the second interconnect.

4 . The system as claimed in claim 1 wherein:

connecting the first integrated circuit die comprises:

connecting the first integrated circuit die on the first side, and

attaching an external interconnect on the first side; and

further comprising:

forming a bottom integrated circuit package having a second substrate;

attaching an integrated circuit die on a bottom side of the second substrate; and

attaching the external interconnect on a top side of the second substrate.

5 . The system as claimed in claim 1 wherein:

connecting the first integrated circuit die comprises:

connecting the first integrated circuit die on the first side; and

further comprising:

attaching an external interconnect on the second side;

forming a bottom integrated circuit package having a second substrate with an opening;

connecting an integrated circuit die on a bottom side of the second substrate to a top side of the second substrate through the opening; and

attaching the external interconnect on the top side.

6 . A multichip package system comprising:

forming a first substrate having a first side, a second side, and a first opening;

connecting a first integrated circuit die on the first side to the second side through the first opening;

connecting a second integrated circuit die on the first substrate; and

encapsulating the first integrated die and second integrated circuit die on the first substrate.

7 . The system as claimed in claim 6 wherein connecting the first integrated circuit die comprises attaching the first integrated circuit die having an active side on the first side with an adhesive.

8 . The system as claimed in claim 6 wherein connecting the first integrated circuit die comprises:

forming a bonding pad in a central region of an active side of the first integrated circuit die; and

connecting the bonding pad to the second side.

9 . The system as claimed in claim 6 wherein connecting the second integrated circuit die comprises:

forming a bonding pad in a central region of an active side of the second integrated circuit die; and

connecting the bonding pad to the second side.

10 . The system as claimed in claim 6 wherein encapsulating includes filling the first opening.

11 . A multichip package system comprising:

a first substrate having a first side, a second side, and a first opening;

a first integrated circuit die connected to the first substrate through the first opening;

a second integrated circuit die on the first substrate; and

a mold compound to cover the first integrated die and second integrated circuit die on the first substrate.

12 . The system as claimed in claim 11 wherein:

the first integrated circuit die to the first substrate through the first opening comprises:

an active side of the first integrated circuit die on the first side, and

an interconnect between the active side and the second side;

the second integrated circuit die further comprises:

the second integrated circuit die on the second side at one side of the first opening; and

further comprising:

a third integrated circuit die on the second side at an opposite side of the first opening; and

the mold compound to cover the interconnect.

13 . The system as claimed in claim 11 further comprising:

the first substrate have a second opening;

a first active side of the first integrated circuit die on the first side;

a first interconnect between the first active side and the second side;

a second active side of the second integrated circuit die on the first side;

a second interconnect between the second active side and the second side through the second opening; and

the mold compound to cover the first interconnect and the second interconnect.

14 . The system as claimed in claim 11 wherein:

the first integrated circuit die comprises:

the first integrated circuit die on the first side, and

an external interconnect on the first side; and

further comprising:

a bottom integrated circuit package having a second substrate;

an integrated circuit die on a bottom side of the second substrate; and

the external interconnect on a top side of the second substrate.

15 . The system as claimed in claim 11 wherein:

the first integrated circuit die comprises:

the first integrated circuit die on the first side; and

further comprising:

an external interconnect on the second side;

a bottom integrated circuit package having a second substrate with an opening;

an integrated circuit die on a bottom side of the second substrate connected to a top side of the second substrate through the opening; and

the external interconnect on the top side.

16 . The system as claimed in claim 11 wherein:

the first substrate having the first side, the second side, and the first opening provides signal routing;

the first integrated circuit die is on the first side and connected to the second side through the first opening;

the second integrated circuit die on the first substrate is electrically connected to the first substrate; and

the mold compound to cover the first integrated die and second integrated circuit die on the first substrate is an epoxy mold compound.

17 . The system as claimed in claim 16 wherein the first integrated circuit die on the first side is attached to the first side with an adhesive.

18 . The system as claimed in claim 16 wherein the first integrated circuit die on the first side comprises:

a bonding pad in a central region of an active side of the first integrated circuit die; and

the bonding pad connected to the second side.

19 . The system as claimed in claim 16 wherein the second integrated circuit die on the first substrate comprises:

a bonding pad in a central region of an active side of the second integrated circuit die; and

the bonding pad connected to the second side.

20 . The system as claimed in claim 16 wherein the mold compound fills the first opening.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Jun 17, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 053476/0094 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR'S NAME PREVIOUSLY RECORDED ON REEL 038378 FRAME 0442. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Jul 26, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 039514/0451 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 17, 2006
From: CHOI, SUNGWON; JEONG, TAE SUNG
To: STATS CHIPPAC LTD.
Reel/Frame 017485/0003 →