Flip chip interconnection having narrow interconnection sites on the substrate
A flip chip interconnect of a die on a substrate is made by mating the interconnect bump onto a narrow interconnect pad on a lead or trace, rather than onto a capture pad. The width of the narrow interconnect pad is less than a base diameter of bumps on the die to be attached. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having narrow interconnect pads on electrically conductive traces in a die attach surface, in which the bumps are mated onto the narrow pads on the traces.
1 . A flip chip interconnection, comprising a solder bump attached to an interconnect pad on a die and mated onto a pad at an interconnect site on a substrate, wherein a width of the pad at the interconnect site is less than a nominal width of the contact interface between the bump and the die pad.
2 . The flip chip interconnection of claim 1 wherein the width of the pad at the interconnect site is at least about 20% as great as the nominal width of the contact interface between the bump and the die pad.
3 . The flip chip interconnection of claim 1 wherein the width of the pad at the interconnect site is at least about 25% as great as the nominal width of the contact interface between the bump and the die pad.
4 . The flip chip interconnection of claim 2 wherein the width of the pad at the interconnect site is less than about 80% as great as the nominal width of the contact interface between the bump and the die pad.
5 . The flip chip interconnection of claim 2 wherein the width of the pad at the interconnect site is less than about 60% as great as the nominal width of the contact interface between the bump and the die pad.
6 . The flip chip interconnection of claim 1 wherein the width of the pad at the interconnect site is greater than about 120% of a trace design rule width.
7 . A flip chip interconnection, comprising a solder bump attached to an interconnect pad on a die and mated onto a pad at an interconnect site on a substrate, wherein a width of the pad at the interconnect site is less than a design width of the contact interface between the bump and the die pad.
8 . The flip chip interconnection of claim 7 wherein the width of the pad at the interconnect site is at least about 20% as great as the design width of the contact interface between the bump and the die pad.
9 . The flip chip interconnection of claim 7 wherein the width of the pad at the interconnect site is at least about 25% as great as the design width of the contact interface between the bump and the die pad.
10 . The flip chip interconnection of claim 8 wherein the width of the pad at the interconnect site is less than about 80% as great as the design width of the contact interface between the bump and the die pad.
11 . The flip chip interconnection of claim 8 wherein the width of the pad at the interconnect site is less than about 60% as great as the design width of the contact interface between the bump and the die pad.
12 . The flip chip interconnection of claim 1 wherein the width of the pad at the interconnect site is greater than about 120% of a nominal trace width.
13 . A flip chip semiconductor package comprising a plurality of solder bumps each attached to an interconnect pad on a die and mated onto a corresponding a pad at an interconnect site on a substrate, wherein a width of the pad at the interconnect site is less than a nominal width of the contact interface between the bump and the die pad.
14 . The flip chip semiconductor package of claim 13 wherein the width of the pad at the interconnect site is at least about 20% as great as the nominal width of the contact interface between the bump and the die pad.
15 . The flip chip semiconductor package of claim 13 wherein the width of the pad at the interconnect site is at least about 25% as great as the nominal width of the contact interface between the bump and the die pad.
16 . The flip chip semiconductor package of claim 14 wherein the width of the pad at the interconnect site is less than about 80% as great as the nominal width of the contact interface between the bump and the die pad.
17 . The flip chip semiconductor package of claim 14 wherein the width of the pad at the interconnect site is less than about 60% as great as the nominal width of the contact interface between the bump and the die pad.
18 . The flip chip semiconductor package of claim 14 wherein the width of the pad at the interconnect site is greater than about 120% of a nominal trace width.
19 . A flip chip semiconductor package comprising a plurality of solder bumps each attached to an interconnect pad on a die and mated onto a corresponding a pad at an interconnect site on a substrate, wherein a width of the pad at the interconnect site is less than a design width of the contact interface between the bump and the die pad.
20 . The flip chip semiconductor package of claim 19 wherein the width of the pad at the interconnect site is at least about 20% as great as the design width of the contact interface between the bump and the die pad.
21 . The flip chip semiconductor package of claim 19 wherein the width of the pad at the interconnect site is at least about 25% as great as the design width of the contact interface between the bump and the die pad.
22 . The flip chip semiconductor package of claim 20 wherein the width of the pad at the interconnect site is less than about 80% as great as the design width of the contact interface between the bump and the die pad.
23 . The flip chip semiconductor package of claim 20 wherein the width of the pad at the interconnect site is less than about 60% as great as the design width of the contact interface between the bump and the die pad.
24 . The flip chip semiconductor package of claim 20 wherein the width of the pad at the interconnect site is greater than about 120% of a nominal trace width.
25 . The flip chip interconnection of claim 1 , the interconnection being non-solder mask defined.
26 . The flip chip interconnection of claim 1 , the interconnection being solder mask defined.
27 . A substrate for flip chip interconnection of a die, the die having a bumps each attached on a die pad, the substrate comprising a patterned metal layer having pads at interconnect sites, wherein a width of a said pad at a said interconnect site is less than a nominal width of a contact interface between a said bump and the die pad.
28 . The substrate of claim 27 wherein the width of the pad at the interconnect site is at least about 20% as great as the nominal width of the contact interface between the bump and the die pad.
29 . The substrate of claim 27 wherein the width of the pad at the interconnect site is at least about 25% as great as the nominal width of the contact interface between the bump and the die pad.
30 . The substrate of claim 28 wherein the width of the pad at the interconnect site is less than about 80% as great as the nominal width of the contact interface between the bump and the die pad.
31 . The substrate of claim 28 wherein the width of the pad at the interconnect site is less than about 60% as great as the nominal width of the contact interface between the bump and the die pad.
32 . The substrate of claim 28 wherein the width of the pad at the interconnect site is greater than about 120% of a trace design rule width.
33 . A method for forming a flip chip interconnection, comprising providing a substrate as recited in claim 27; supporting the substrate and the die; dispensing a quantity of a curable adhesive on the substrate; positioning the die with the active side of the die toward the die attach surface of the substrate, and aligning the die and substrate and moving one toward the other so that the bumps contact the corresponding narrow interconnection pads on the substrate; applying a force to press the bumps onto the mating narrow pads, sufficient to displace the adhesive from between the bump and the mating narrow pad; at least partially curing the adhesive; melting and then re-solidifying the solder, forming a metallurgical interconnection between the bump and the pad.
34 . The method of claim 33 wherein dispensing a quantity of a curable adhesive on the substrate covers at least the interconnection pads on the substrate.