Method and apparatus of core timing prediction of core logic in the chip-level implementation process through an over-core window on a chip-level routing layer
A method and/or an apparatus of core timing prediction is disclosed. In one embodiment, a method may include generating a core timing model of a core logic that is accurately transferable to any chip-level integration process. The method may reduce performance degradation and/or performance variation of the core logic caused by a number of interactions between core logic components and chip-level components in the chip-level integration process. In addition, the core timing model of the core logic may be generated by filling un-wired tracks with metal in any of an outermost layer of the core logic after a core logic routing and constructing a layer at least an area of and adjacent to any of the outermost layer of the core logic with grounded metal that is orthogonal to those of the metal used in the outermost layer of the core logic.
1. A method, comprising:
generating a core timing model of a core logic that is accurately transferable to any chip-level integration process using a processor,
wherein there is an over-core window on a chip-level routing layer;
reducing any of a performance degradation and performance variation of the core logic caused by a plurality of interactions between core logic components and chip-level components in the chip-level integration process,
wherein to minimize impact of a parasitic environment of the core logic in which the core timing model of the core logic generated is reduced by grounded metal; and
reducing any of a cross-talk effect and a capacitive coupling effect and modeling any of a timing change and a behavior change due to any of a residual cross-talk effect and a residual capacitive coupling effect.
2. The method of claim 1 further comprising generating the core timing model of the core logic after metal filling un-wired tracks in any of an outermost layer of the core logic after a core logic routing.
3. The method of claim 2 further comprising constructing a core logic layer and any of a chip-level routing layer, having routes that are thinner and routes that are thicker, with the grounded metal of physical characteristics typical for routing in the layer,
wherein the grounded metal resides within a core window substantially similar to an area of the core logic, and
wherein no routing takes place within the over-core window of any of the chip-level routing layer.
4. The method of claim 1 further comprising constructing the parasitic environment of the core logic caused by a plurality of interactions between core logic components and chip-level components preceding any chip-level integration process.
5. The method of claim 4 further comprising reproducing the parasitic environment of the core logic caused by any of the plurality of interactions between core logic components and chip-level components during any chip-level integration process.
6. The method of claim 1 further comprising generating the core timing model of the core logic to represent any over-core routing of any chip-level components preceding the chip-level integration process.
7. The method of claim 6 further comprising decreasing a variation range of the core timing model to represent the over-core routing of any of the chip-level components.
8. The method of claim 1 further comprising mitigating a fabrication process variation at the chip-level integration process on the accuracy of the core timing model.
9. A method, comprising:
generating a core timing model of a core logic that is accurately transferable to any chip-level integration process using a processor,
wherein there is an over-core window on a chip-level routing layer;
reducing any of a performance degradation and performance variation of the core logic caused by a plurality of interactions between core logic components and chip-level components in the chip-level integration process,
wherein to minimize impact of a parasitic environment of the core logic in which the core timing model of the core logic generated is reduced by grounded metal;
reducing any of a cross-talk effect and a capacitive coupling effect and modeling any of a timing change and a behavior change due to any of a residual cross-talk effect and a residual capacitive coupling effect; and
mitigating a fabrication process variation at any chip-level integration process on the accuracy of the core timing model.
10. The method of claim 9 further comprising generating the core timing model of the core logic after metal filling un-wired tracks in any of an outermost layer of the core logic after a core logic routing.
11. The method of claim 9 further comprising constructing
a core logic layer and any of a chip-level routing layer, having routes that are thinner and routes that are thicker, with the grounded metal of physical characteristics typical for routing in the layer,
wherein the grounded metal resides within a core window substantially similar to an area of the core logic, and
wherein no routing takes place within the over-core window of any of the chip-level routing layer.
12. The method of claim 9 further comprising constructing the parasitic environment of the core logic caused by a plurality of interactions between core logic components and chip-level components preceding any chip-level integration process.
13. The method of claim 12 further comprising reproducing the parasitic environment of the core logic caused by any of the plurality of interactions between core logic components and chip-level components during any chip-level integration process.
14. The method of claim 9 further comprising generating the core timing model of the core logic to represent any over-core routing of any chip-level components preceding the chip-level integration process.
15. The method of claim 14 further comprising decreasing a variation range of the core timing model to represent the over-core routing of any of the chip-level components.