IP Library Granted Patent US 7,639,768
Granted Patent B1
US 7,639,768 · App. 11/414,845 · Granted Dec 29, 2009

Method for improving performance in a mobile device

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Quick Facts
Patent No.
US 7,639,768
App. No.
11/414,845
Granted
Dec 29, 2009
Kind
B1
Abstract

In the operation of a mobile device (such as a cellular telephone or a PDA, i.e. Personal Digital Assistant), which mobile device includes a mobile terminal and a memory module, certain operational signals of the mobile device are multiplexed and demultiplexed, resulting in efficient device bus utilization and reduced device pin count.

Claims (15)

1. A method of memory access of a mobile terminal for use with a memory module external to the mobile terminal and comprising first and second memories, the method comprising providing a first address control signal for the first memory by means of a first address control signal generator, and a second address control signal for the second memory by means of a second address control signal generator, the first address control signal being capable of first and second states, the second address control signal being capable of first and second states, the respective first states of the first and second address control signals not overlapping in time, wherein the first states of the first and second address control signals provide the mobile terminal operative access of the first and second memories, respectively and the second states of the first and second address control signals prevent mobile terminal operative access of the first and second memories, respectively.

2. The method of claim 1 wherein the respective first states of the first and second address signals are provided on different clock cycles.

3. The method of claim 2 wherein the respective first states of the first and second address control signals are provided on successive clock cycles.

4. The method of claim 1 wherein the first and second address control signals are provided on a common bus.

5. The method of claim 1 wherein the first and second memories are dynamic and static memories respectively.

6. The method of claim 1 wherein the first address control signal is provided to a multiplexer.

7. The method of claim 1 wherein the second address control signal is provided to a multiplexer.

8. The method of claim 1 wherein the first address control signal is provided to a first multiplexer of the mobile terminal, and the second address control signal is provided to a second multiplexer of the mobile terminal.

9. The method of claim 8 wherein the first address control signal is provided to the first multiplexer as select signal, and the second address control signal is provided to the second multiplexer as a select signal.

10. A method of memory access of a mobile terminal for use with a memory module external to the mobile terminal and in operative association therewith, the method comprising providing a plurality of signals by means of signal providing means, and, by means of multiplexing means, multiplexing some of the plurality of signals and not multiplexing others of the plurality of signals, wherein the multiplexing means provides the mobile terminal operative access of a first memory and a second memory of the memory module, wherein the multiplexed signals to the first memory and the multiplexed signals to the second memory do not overlap in time.

11. The method of claim 10 and further comprising demultiplexing the multiplexed signals.

12. The method of claim 10 wherein the multiplexed signals comprise memory control signals.

13. The method of claim 12 wherein the signals not multiplexed comprise data signals.

14. The method of claim 13 wherein the multiplexed signals comprise signals for controlling the first memory and signals for controlling the second memory.

15. The method of claim 14 wherein the signals for controlling the first memory are dynamic memory control signals, and the signals for controlling the second memory are static control signals.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 16, 2025
From: MONTEREY RESEARCH LLC
To: SOUTHFORK IP HOLDINGS LLC
Reel/Frame 071299/0161 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036049/0581 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 1, 2006
From: HASAN, QAMRUI; MAH, JEREMY; ROSNER, STEPHAN
To: SPANSION LLC
Reel/Frame 017847/0958 →