IP Library Granted Patent US 7,541,238
Granted Patent B2
US 7,541,238 · App. 11/414,902 · Granted Jun 2, 2009

Inductor formed in an integrated circuit

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Quick Facts
Patent No.
US 7,541,238
App. No.
11/414,902
Filed
May 1, 2006
Granted
Jun 2, 2009
Kind
B2
Art Unit
2832
USPC
336/210
Abstract

An inductor formed within an integrated circuit and a method for forming the inductor. The inductor comprises an underlying layer of aluminum formed in a first metallization layer and patterned and etched into the desired shape. In one embodiment the aluminum line comprises a spiral shape. According to a damascene process, a conductive runner, preferably of copper, is formed in a dielectric layer overlying the aluminum line and in electrical contact therewith. The aluminum line and the conductive runner cooperate to form the inductor. In another embodiment the aluminum line and the conductive runner are formed in a vertically spaced-apart orientation, with tungsten plugs or conductive vias formed to provide electrical connection therebetween. A method for forming the inductor comprises forming an aluminum conductive line and forming a conductive runner over the conductive line.

Claims (21)

1. A method for forming an inductor in a semiconductor integrated circuit, the method comprising:

forming a conductive line in a metallization layer;

forming a first dielectric layer overlying the conductive line;

forming conductive structures in the first dielectric layer;

forming a conductive pad overlying and in electrical communication with one of the conductive structures and a terminal end of the conductive line;

forming a second dielectric layer overlying the first dielectric layer and the conductive pad;

forming a trench in the second dielectric layer; and

forming a conductive runner in the trench, wherein the conductive runner is in conductive communication with the conductive line through the conductive structures, and wherein the conductive line and the conductive runner cooperate to produce an inductive effect.

2. The method of claim 1 wherein forming the conductive line further comprises:

forming a conductive layer; and

removing regions of the conductive layer to form the conductive line.

3. The method of claim 2 wherein forming the conductive layer further comprise forming an aluminum conductive layer.

4. The method of claim I wherein forming the conductive runner in the trench further comprises depositing copper in the trench.

5. The method of claim 4 wherein depositing copper in the trench further comprises electroplating copper in the trench.

6. The method of claim 1 wherein forming the trench in the dielectric layer further comprises forming the trench in vertical alignment with the conductive line.

7. The method of claim 1 wherein forming the trench in the dielectric layer further comprises forming the trench in vertical alignment with the conductive line.

8. The method of claim 1 further comprising:

forming an opening in the second dielectric layer extending to the conductive pad;

forming a conductive structure in the opening, wherein the conductive structure forms an inductor terminal.

9. The method of claim 8 wherein forming the conductive structure further comprises forming a solder bump.

10. The method of claim 8 wherein forming the conductive structure further comprises forming a bond pad.

Assignments (8)
SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 060885/0001 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →