Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop

1. A programmable logic cell comprising:

a logic circuit having three inputs and at least one output;

a first multiplexer, a second multiplexer, and a third multiplexer, each of said first second and third multiplexers having two inputs and an output; and

a plurality of programmable elements coupled between said three inputs and at least one output of said logic circuit and said two inputs and said outputs of said first, second, and third multiplexers such that a plurality of sequential logic units and combinatorial units can be realized by programming selected ones of said programmable elements, wherein said sequential logic units include a flip-flop.

2. The programmable logic cell of claim 1 , further comprising:

a NAND gate coupled between at least two of said multiplexers; and

a plurality of inverters coupled between said three inputs and at least one output of said logic circuit.

3. The programmable logic cell of claim 1 , wherein the programmable elements comprise flash transistors.

4. The programmable logic cell of claim 1 , wherein the programmable elements comprise antifuse elements.

5. The programmable logic cell of claim 1 , wherein the programmable elements comprise MOS transistors.

6. The programmable logic cell of claim 1 , wherein said flip-flop is a D flip-flop.

7. The programmable logic cell of claim 1 , wherein said combinatorial units include a look-up table.

8. The programmable logic cell of claim 7 , wherein said look-up table is a three-input look-up table.

9. The programmable logic cell of claim 1 , wherein said sequential logic units include a D latch.