Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks
View Patent ↗A repeatable non-uniform segmented routing architecture in a field programmable gate array comprising: a repeatable block of routing tracks, the routing tracks grouped into sets of routing tracks, each set having a first routing track in a first track position, a second routing track in a last track position, a programmable element, and a direct address device for programming the programmable element; wherein at least one of the routing tracks is segmented into non-uniform lengths by the programmable element and the second routing track crosses-over to the first track position in a region adjacent to an edge of the repeatable block; and wherein a first plurality of the routing track sets proceed in a horizontal direction and a second plurality of the routing track sets proceed in a vertical direction.
1. A repeatable non-uniform segmented routing architecture in a field programmable gate array comprising:
a repeatable block of routing tracks, the routing tracks grouped into sets of routing tracks, each set having a first routing track in a first track position, a second routing track in a last track position, a programmable element, and a direct address device for programming said programmable element;
wherein at least one of said routing tracks is segmented into non-uniform lengths by said programmable element and said second routing track crosses-over to said first track position in a region adjacent to an edge of said repeatable block; and
wherein a first plurality of said routing track sets proceed in a horizontal direction and a second plurality of said routing track sets proceed in a vertical direction.
2. The routing architecture of claim 1 , wherein said first plurality and said second plurality of routing track sets are disposed on the same layer on a die.
3. The routing architecture of claim 1 , wherein said programmable element comprises an antifuse.
4. The routing architecture of claim 1 , wherein said direct address device comprises a pass transistor.
5. The routing architecture of claim 1 , wherein each set of routing tracks in said first plurality of said routing track sets further comprises an additional routing track disposed in between said first routing track and said second routing track.
6. The routing architecture of claim 5 , wherein said second routing track of said first plurality of said routing track sets crosses-over said additional routing track and said first routing track of said first plurality of said routing track sets to said first track position in a region adjacent to an edge of said repeatable block.
7. The routing architecture of claim 1 , wherein each set of routing tracks in said second plurality of said routing track sets further comprises an additional routing track disposed in between said first routing track and said second routing track.
8. The routing architecture of claim 7 , wherein said second routing track of said second plurality of said routing track sets crosses-over said additional routing track and said first routing track of said second plurality of said routing track sets to said first track position in a region adjacent to an edge of said repeatable block.
9. The routing architecture of claim 1 , wherein said first plurality of said routing track sets is disposed between logic cluster columns on said field programmable gate array.
10. The routing architecture of claim 1 , wherein said second plurality of said routing track sets extends directly into input/output cluster columns on said field programmable gate array.
11. The routing architecture of claim 1 , wherein said first plurality and said second plurality of said routing track sets provide interconnections between logic clusters on said field programmable gate array.
12. The routing architecture of claim 1 , wherein said programmable element is one-time programmable.
13. The routing architecture of claim 1 , wherein said programmable element is re-programmable.