IP Library Granted Patent US 7,629,220
Granted Patent B2
US 7,629,220 · App. 11/428,038 · Granted Dec 8, 2009

Method for forming a semiconductor device and structure thereof

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Quick Facts
Patent No.
US 7,629,220
App. No.
11/428,038
Granted
Dec 8, 2009
Kind
B2
Abstract

A non-planar semiconductor device ( 10 ) starts with a silicon fin ( 42 ). A source of germanium (e.g. 24, 26, 28, 30, 32 ) is provided to the fin ( 42 ). Some embodiments may use deposition to provide germanium; some embodiments may use ion implantation ( 30 ) to provide germanium; other methods may also be used to provide germanium. The fin ( 42 ) is then oxidized to form a silicon germanium channel region in the fin ( 36 ). In some embodiments, the entire fin ( 42 ) is transformed from silicon to silicon germanium. One or more fins ( 36 ) may be used to form a non-planar semiconductor device, such as, for example, a FINFET, MIGFET, Tri-gate transistor, or multi-gate transistor.

Claims (40)

1. A method for forming a non-planar semiconductor device, comprising:

forming a fin, a first current electrode, and a second current electrode of the non-planar semiconductor device, wherein the fin, the first current electrode, and the second current electrode each comprises silicon;

providing a source of germanium to the fin, to the first current electrode, and to the second current electrode,

wherein providing the source of germanium to the fin comprises implanting the fin with germanium;

oxidizing to distribute the germanium throughout the fin, to form an inner region and an outer region of the first current electrode, and to form an inner region and an outer region of the second current electrode, wherein the outer region of the first electrode comprises germanium but the inner region of the first electrode does not comprise germanium, and wherein the outer region of the second current electrode comprises germanium but the inner region of the second electrode does not comprise germanium; and

completing formation of the non-planar semiconductor device.

2. A method as in claim 1 , wherein implanting the fin with germanium comprises using an implant angle in a range of 30 degrees to 10 degrees.

3. A method as in claim 1 , wherein said step of implanting the fin with germanium comprises:

using a germanium atom dose in a range of 5×10e13 to 5×10e16.

4. A method as in claim 1 , wherein said step of implanting the fin with germanium comprises:

using an ion implant energy in a range of 1 keV to 120 keV.

5. A method as in claim 1 , wherein said step of providing the source of germanium to the fin comprises:

forming a silicon germanium layer on the sidewalls of the fin.

6. A method as in claim 1 , wherein an insulating layer overlies at least a portion of the fin.

7. A method as in claim 1 , wherein the non-planar semiconductor device is formed using a wafer portion comprising a first insulating layer overlying a substrate, a monocrystalline semiconductor layer overlying the first insulating layer, and a second insulating layer overlying the monocrystalline semiconductor layer.

8. A method as in claim 1 , further comprising:

after said step of forming the fin and before said step of providing the source of germanium, forming a silicon nitride layer overlying the fin.

9. A method as in claim 1 , further comprising:

after said step of oxidizing the fin, etching at least a portion of silicon dioxide formed during the oxidation step.

10. A method as in claim 1 , wherein the channel region comprises all of the fin.

11. A method as in claim 1 , wherein the non-planar semiconductor device comprises a FINFET.

12. A method as in claim 1 , wherein the non-planar semiconductor device comprises a MIGFET.

13. A method as in claim 1 , wherein the non-planar semiconductor device comprises a Tri-gate transistor.

14. A method for forming a non-planar semiconductor device, comprising:

forming a fin, a first current electrode, and a second current electrode of the non-planar semiconductor device, wherein the fin, the first current electrode, and the second current electrode each comprises silicon;

providing a source of germanium to the fin, to the first current electrode, and to the second current electrode;

oxidizing to distribute the germanium throughout the fin, to form an inner region and an outer region of the first current electrode, and to form an inner region and an outer region of the second current electrode, wherein the outer region of the first electrode comprises germanium but the inner region of the first electrode does not comprise germanium, and wherein the outer region of the second current electrode comprises germanium but the inner region of the second electrode does not comprise germanium; and

completing formation of the non-planar semiconductor device.

15. A method as in claim 14 , further comprising:

removing at least a portion of an oxide formed during said step of oxidizing.

16. A method as in claim 14 , wherein the non-planar semiconductor device comprises a FINFET.

17. A method as in claim 14 , wherein the non-planar semiconductor device comprises a MIGFET.

18. A method for forming a non-planar semiconductor device, comprising:

forming a fin, a first current electrode, and a second current electrode of the non-planar semiconductor device, wherein the fin, the first current electrode, and the second current electrode each comprises silicon;

providing a source of germanium to the fin, to the first current electrode, and to the second current electrode;

oxidizing to distribute the germanium throughout the fin, to form an inner region and an outer region of the first current electrode, and to form an inner region and an outer region of the second current electrode, wherein the outer region of the first electrode comprises germanium but the inner region of the first electrode does not comprise germanium, and wherein the outer region of the second current electrode comprises germanium but the inner region of the second electrode does not comprise germanium; and

completing formation of the non-planar semiconductor device,

wherein the non-planar semiconductor device is formed using a wafer portion comprising a first insulating layer overlying a substrate, a monocrystalline semiconductor layer overlying the first insulating layer, and a second insulating layer overlying the monocrystalline semiconductor layer.

19. A method as in claim 18 , wherein said step of providing the source of germanium to the fin comprises forming a silicon germanium layer on the sidewalls of the fin, and wherein said step of forming the silicon germanium layer on the sidewalls of the fin comprises deposition of silicon germanium.

20. A method as in claim 19 , wherein the deposition of silicon germanium is selective.

Assignments (23)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037355/0723 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Mar 15, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 024079/0082 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2006
From: ORLOWSKI, MR. MARIUS K.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 017862/0425 →