Method for wafer level chip scale packaging with passive components integrated into packaging structure
View Patent ↗The present invention provides a Wafer Level Chip Scale Packaging structure including a die, at least one passive component, a combining layer, an isolating layer, at least one connecting wire, an internal pad and a passivation layer. The die includes a shallow connecting pad, an internal pad and an electrical component. The passive component is formed on one side of the die. The combining layer increases the binding force between the passive component and the die. The part surface on the other side of the die is overlaid with the isolation layer. The part surface of the isolation layer and the internal pad is overlaid with the connecting wire to electrically connect to the internal pad, and the passivation layer is used for protecting the die.
1. An integrated wafer packaging method, comprising: forming an interfacing layer on a surface, comprising a shallow connecting pad, of a wafer; forming a photo resist layer comprising at least an opening in a proximate area of a corresponding area of the shallow connecting pad, wherein the opening defines a shape and a size of at least a passive component; forming at least a passive component on the at least an opening and then removing the photo resist layer; forming a masking layer on another surface of the wafer, wherein the masking layer comprising at least an opening in the proximate area of the corresponding location of an internal connecting pad; coating an electricity isolating material on the surface of the wafer and covering at least a passive component to form a combining layer; combining a passivation layer with the combining layer; etching the another surface of the wafer to remove an unmasked portion of the wafer to form at least a wafer opening connected to at least an internal connecting pad; removing the masking layer; forming an isolation layer on the another surface of the wafer; and forming a connecting wire layout over the isolation layer.
2. The integrated wafer packaging method according to the claim 1 , wherein the interfacing layer forming step further comprises: forming a barrier layer; and forming a seed layer.
3. The integrated wafer packaging method according to the claim 2 , wherein the etching process comprises: an isotropic etching, forming at least an expanded wafer opening; an anisotropic etching, forming a wafer opening toward the outside, wherein the wafer toward the outside is a bow-shaped opening with an opening area bigger than an bottom area.
4. The integrated wafer packaging method according to the claim 3 , further comprising a wafer thinning process to thin the wafer before forming the masking layer on the another surface of the wafer, wherein the wafer thinning process comprises a polishing process, a CMP, a wet etching, a plasma etching, and a combination thereof.
5. The integrated wafer packaging method according to the claim 2 , further comprising a wafer thinning process to thin the wafer before forming the masking layer on the another surface of the wafer, wherein the wafer thinning process comprises a polishing process, a CMP, a wet etching, a plasma etching, and a combination thereof.
6. The integrated wafer packaging method according to the claim 1 , wherein the etching process comprises: an isotropic etching, forming at least an expanded wafer opening; an anisotropic etching, forming a wafer opening toward the outside, wherein the wafer toward the outside is a bow-shaped opening with an opening area bigger than an bottom area.
7. The integrated wafer packaging method according to the claim 6 , further comprising a wafer thinning process to thin the wafer before forming the masking layer on the another surface of the wafer, wherein the wafer thinning process comprises a polishing process, a CMP, a wet etching, a plasma etching, and a combination thereof.
8. The integrated wafer packaging method according to the claim 1 , further comprising a wafer thinning process to thin the wafer before forming the masking layer on the another surface of the wafer, wherein the wafer thinning process comprises a polishing process, a CMP, a wet etching, a plasma etching, and a combination thereof.
9. The integrated wafer packaging method according to the claim 1 , wherein the passive component comprises an inductive device.
10. The integrated wafer packaging method according to the claim 1 , wherein the passive component comprises a capacitive device.
11. The integrated wafer packaging method according to the claim 1 , wherein the passive component comprises a resistive device.
12. The integrated wafer packaging method according to the claim 1 , wherein the passive component comprises a resistive device.
13. An integrated wafer packaging method, comprising: forming a photo resist layer on a surface, comprising a shallow connecting pad, of a wafer; wherein the photo resist layer comprising at least an opening in a proximate area of a corresponding area of the shallow connecting pad, wherein the opening defines a shape and a size of at least a passive component; forming at least a passive component on the at least an opening and then removing the photo resist layer, wherein the combining layer reduces the stress between the at least a passive component and the shallow connecting pad; forming a masking layer on another surface of the wafer, wherein the masking layer comprising at least an opening in the proximate area of the corresponding location of an internal connecting pad; coating an electricity isolating material on the surface of the wafer and covering at least a passive component to form a combining layer; combining a passivation layer with the combining layer; etching the another surface of the wafer to remove an unmasked portion of the wafer to form at least a wafer opening connected to at least an internal connecting pad; removing the masking layer; forming an isolation layer on the another surface of the wafer; and forming a connecting wire layout over the isolation layer.
14. The integrated wafer packaging method according to the claim 13 , wherein the interfacing layer forming step further comprises: forming a barrier layer; and forming a seed layer.
15. The integrated wafer packaging method according to the claim 14 , wherein the etching process comprises: an isotropic etching, forming at least an expanded wafer opening; an anisotropic etching, forming a wafer opening toward the outside, wherein the wafer toward the outside is a bow-shaped opening with an opening area bigger than an bottom area.
16. The integrated wafer packaging method according to the claim 15 , further comprising a wafer thinning process to thin the wafer before forming the masking layer on the another surface of the wafer, wherein the wafer thinning process comprises a polishing process, a CMP, a wet etching, a plasma etching, and a combination thereof.
17. The integrated wafer packaging method according to the claim 14 , further comprising a wafer thinning process to thin the wafer before forming the masking layer on the another surface of the wafer, wherein the wafer thinning process comprises a polishing process, a CMP, a wet etching, a plasma etching, and a combination thereof.
18. The integrated wafer packaging method according to the claim 13 , wherein the etching process comprises: an isotropic etching, forming at least an expanded wafer opening; an anisotropic etching, forming a wafer opening toward the outside, wherein the wafer toward the outside is a bow-shaped opening with an opening area bigger than an bottom area.
19. The integrated wafer packaging method according to the claim 18 , further comprising a wafer thinning process to thin the wafer before forming the masking layer on the another surface of the wafer, wherein the wafer thinning process comprises a polishing process, a CMP, a wet etching, a plasma etching, and a combination thereof.
20. The integrated wafer packaging method according to the claim 13 , further comprising a wafer thinning process to thin the wafer before forming the masking layer on the another surface of the wafer, wherein the wafer thinning process comprises a polishing process, a CMP, a wet etching, a plasma etching, and a combination thereof.
21. The integrated wafer packaging method according to the claim 13 , wherein the passive component comprises an inductive device.
22. The integrated wafer packaging method according to the claim 13 , wherein the passive component comprises a capacitive device.