IP Library Granted Patent US 7,703,059
Granted Patent B2
US 7,703,059 · App. 11/438,644 · Granted Apr 20, 2010

Method and apparatus for automatic creation and placement of a floor-plan region

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,703,059
App. No.
11/438,644
Granted
Apr 20, 2010
Kind
B2
Abstract

A method and apparatus for floor-plan region creation and placement is provided. Design information may be received. Module area may be estimated for each module in an integrated circuit. Individual module may be selected for regioning, and region size and dimensions for module may be determined. Region parameters may be adjusted prior to final placement and placement may be verified.

Claims (45)

1. A computer-readable medium having computer-executable instructions for performing a method for creating and placing a floor-plan region, said method comprising:

receiving design information for an integrated circuit, said integrated circuit being comprised of a plurality of modules and said design

information including connectivity information regarding said plurality of modules;

calculating an area estimate for a module of said plurality of modules from said received design information, the area estimate excluding the area of a fixed cell or blockage within said module;

selecting a module to place within a region suitable for encompassing said module;

calculating region size for the region suitable for encompassing said module by utilizing said area estimate calculated for said module;

determining region dimensions for said region;

selecting an initial region placement by utilizing received connectivity information for said module, the initial region placement positioned in proximity to a fixed cell without encapsulating said fixed cell;

providing region parameter adjustment, further including:

determining a region utilization level;

increasing the region utilization level to a maximum utilization level, further including:

reducing said region dimensions until the maximum utilization level is reached;

determining a number of blockages or fixed cells having one or more horizontal edge components exposed into a region;

determining a number of blockages or fixed cells having one or more vertical edge components exposed into a region; and

increasing at least one of a vertical dimension component or a horizontal dimension component of said region to exclude the blockages or fixed cells and decreasing the other of the at least one of a vertical dimension component or a horizontal dimension component to maintain the area of said region;

scanning said region having said adjusted region parameters to detect a fixed cell horizontal or vertical edge exposure or a blockage present within said region; and,

if a fixed cell horizontal or vertical edge exposure or a blockage is present within the region, increasing the region utilization level and reducing said region dimensions until the increased utilization level is reached;

and

providing placement of said region having said adjusted region parameters.

2. The method as claimed in claim 1 , wherein said design information is received from design RTL code, a netlist, or design instructions.

3. The method as claimed in claim 1 , wherein said region size is determined from inputs including said area estimate and a utilization value.

4. The method as claimed in claim 1 , wherein said region dimensions include at least two adjustable horizontal dimension components and at least two adjustable vertical dimension components.

5. The method as claimed in claim 1 , wherein said module connectivity information includes module periphery connectivity information and pre-placed object connectivity information.

6. The method as claimed in claim 1 , wherein said region parameter adjustment includes at least one of utilization level adjustment, region dimension adjustment and overlap prevention adjustment.

7. A computer based design tool for creating and placing a floor-plan region, wherein said design tool is configured to:

receive design information for an integrated circuit, said integrated circuit being comprised of a plurality of modules, and said design

information including connectivity information regarding said plurality of modules;

estimate an area for at least one of said plurality of modules, the area estimate excluding the area of a fixed cell or blockage within said module;

select a module from said plurality of modules;

calculate region dimensions for a region for said module;

select initial region placement;

provide region parameter adjustment including an adjustment of at least one of region dimensions, region area, region shape, or region utilization requirements, the region parameter adjustment being utilized for fitting the module to a context in a vicinity of a placement point, the region parameter adjustment further including:

determining a region utilization level;

increasing the region utilization level to a maximum utilization level, further including:

reducing said region dimensions until the maximum utilization level is reached;

determining a number of blockages or fixed cells having one or more horizontal edge components exposed into a region;

determining a number of blockages or fixed cells having one or more vertical edge components exposed into a region; and

increasing at least one of a vertical dimension component or a horizontal dimension component of said region to exclude the blockages or fixed cells and decreasing the other of the at least one of a vertical dimension component or a horizontal dimension component to maintain the area of said region;

scanning said region having said adjusted region parameters to detect a fixed cell horizontal or vertical edge exposure or a blockage present within said region; and,

if a fixed cell horizontal or vertical edge exposure or a blockage is present within the region, increasing the region utilization level and reducing said region dimensions until the increased utilization level is reached;

verify placement legalization; and

place a region having said adjusted region parameters for said module.

8. The computer-based design tool as claimed in claim 7 , wherein said design information is received from design RTL code, a netlist, or design instructions.

9. The computer-based design tool as claimed in claim 7 , wherein said region dimensions are determined from inputs including said area estimate and a utilization value.

10. The computer-based design tool as claimed in claim 7 , wherein said region dimensions include at least two adjustable horizontal dimension components and at least two adjustable vertical dimension components.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0223 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044887/0109 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
MERGER Recorded Mar 1, 2010
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 024003/0566 →
MERGER Recorded Feb 19, 2008
From: LSI SUBSIDIARY CORP.
To: LSI CORPORATION
Reel/Frame 020548/0977 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2006
From: MURRAY, DANIEL J.; BYRN, JONATHAN W.
To: LSI LOGIC CORPORATION
Reel/Frame 017922/0488 →