IP Library Granted Patent US 7,656,027
Granted Patent B2
US 7,656,027 · App. 11/443,669 · Granted Feb 2, 2010

In-chip structures and methods for removing heat from integrated circuits

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Quick Facts
Patent No.
US 7,656,027
App. No.
11/443,669
Granted
Feb 2, 2010
Kind
B2
Abstract

An in-chip system and method for removing heat from integrated circuits is disclosed. One embodiment is a substrate with a front side and a back side. The front side of the substrate is capable of having formed thereon a plurality of transistors. A plurality of structures within the substrate contain a solid heat conductive media comprising carbon nanotubes and/or a metal, such as copper. At least some of the plurality of structures extend from the back side of the substrate into the substrate. In some embodiments, the carbon nanotubes are formed within the substrate using a catalyst.

Claims (32)

1. An article of manufacture, comprising:

a substrate with a front side and a back side, wherein the front side of the substrate is capable of having formed thereon a plurality of transistors, wherein the substrate is a silicon-on-insulator (SOI) substrate, with a silicon layer on top of an insulating layer on top of a base substrate; and

a plurality of filled cavities within the substrate that contain a solid heat conductive media comprising carbon nanotubes, wherein the plurality of filled cavities have a density of greater than 1 cavity per mm 2 and a first subset of the plurality of filled cavities extend from the back side of the substrate into the substrate, and wherein a second subset of the plurality of filled cavities other than the first subset contact the insulating layer in the silicon-on-insulator (SOI) substrate.

2. An article of manufacture, comprising:

a substrate with a front side and a back side, wherein the front side of the substrate is capable of having formed thereon a plurality of transistors, wherein the substrate is a silicon-on-insulator ( 501 ) substrate with a silicon layer on top of an insulating layer on top of a base substrate; and

a plurality of structures within the substrate that contain a solid heat conductive media comprising carbon nanotubes, wherein a first subset of the plurality of structures extend from the back side of the substrate into the substrate, wherein a second subset of the plurality of structures other than the first subset contact the insulating layer in the silicon-on-insulator (SOI) substrate.

3. The article of manufacture of claim 2 , wherein the carbon nanotubes are formed within the substrate using a catalyst.

4. The article of manufacture of claim 2 , wherein the structures have a density of greater than 1 per mm 2 .

5. The article of manufacture of claim 2 , wherein the structures comprise filled cavities.

6. The article of manufacture of claim 2 , wherein the base substrate is a silicon substrate.

7. The article of manufacture of claim 2 , wherein at least some of the plurality of structures extend into the insulating layer of the SOI substrate.

8. The article of manufacture of claim 2 , wherein

the article of manufacture comprises an integrated circuit die; and

a plurality of transistors are formed on the front side of the substrate.

9. The article of manufacture of claim 8 , wherein the carbon nanotubes are formed within the substrate using a catalyst.

10. The article of manufacture of claim 8 , wherein the structures have a density of greater than 1 per mm 2 .

11. The article of manufacture of claim 8 , wherein the carbon nanotubes are configured to transfer heat produced by the plurality of transistors to the back side of the substrate.

12. An article of manufacture, comprising:

a heat sink and

an integrated circuit die coupled to the heat sink that includes:

a substrate with a front side and a back side, wherein a plurality of transistors are formed on the front side, wherein the substrate is a silicon-on-insulator (SOI) substrate, with a silicon layer on top of an insulating layer on top of a base substrate; and

a plurality of structures within the substrate that contain a solid heat conductive media comprising carbon nanotubes, wherein a first subset of the plurality of structures extend from the back side of the substrate into the substrate, wherein a second subset of the plurality of structures other than the first subset contact the insulating layer in the silicon-on-insulator (SOI) substrate.

13. The method of claim 12 , wherein at least some of the plurality of structures extend into the insulating layer of the SOI substrate.

14. A method, comprising:

in a substrate with a front side and a back side, wherein the front side of the substrate is capable of having formed thereon a plurality of transistors, wherein the substrate is a silicon-on-insulator ( 501 ) substrate, with a silicon layer on top of an insulating layer on top of a base substrate; and

forming a plurality of structures within the substrate that contain a solid heat conductive media comprising carbon nanotubes, wherein a first subset of the plurality of structures extend from the back side of the substrate into the substrate, wherein a second subset of the plurality of structures other than the first subset contact the insulating layer in the silicon-on-insulator (SOI) substrate.

15. The method of claim 14 , wherein at least some of the plurality of structures extend into the insulating layer of the SOI substrate.

16. A method, comprising:

in a substrate with a front side and a back side, wherein the substrate is a silicon-on-insulator (SOI) substrate, with a silicon layer on top of an insulating layer on top of a base substrate,

generating heat with a plurality of transistors formed on the front side of the substrate; and

conducting at least some of the heat to the back side of the substrate via a plurality of structures within the substrate that contain a solid heat conductive media comprising carbon nanotubes, wherein a first subset of the plurality of structures extend from the back side of the substrate into the substrate, wherein a second subset of the plurality of structures other than the first subset contact the insulating layer in the silicon-on-insulator (SOI) substrate.

17. The method of claim 16 , wherein at least some of the plurality of structures extend into the insulating layer of the SOI substrate.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 28, 2011
From: UNIDYM, INC.
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 025875/0331 →
RELEASE OF SECURITY INTEREST Recorded Jan 10, 2011
From: WOODSIDE FUND V, L.P.; JERUSALEM VENTURE PARTNERS IV, L.P.; JERUSALEM VENTURE PARNTERS IV-A, L.P.; JERUSALEM VENTURE PARTNERS ENTERPRENEURS FUND IV, L.P.; JERUSALEM VENTURE PARTNERS IV (ISRAEL), L.P.
To: UNIDYM, INC.; NANOCONDUCTION, INC.
Reel/Frame 025606/0102 →
RELEASE OF SECURITY INTEREST Recorded Dec 3, 2010
From: NANOCONDUCTION, INC.
To: VENTURE LENDING & LEASING IV, INC.
Reel/Frame 025446/0431 →
RELEASE OF SECURITY INTEREST Recorded Dec 2, 2010
From: VENTURE LENDING & LEASING IV, INC.
To: UNIDYM, INC.
Reel/Frame 025439/0902 →
RELEASE OF SECURITY INTEREST Recorded Dec 2, 2010
From: NANOCONDUCTION, INC.
To: VENTURE LENDING & LEASING IV, INC.
Reel/Frame 025438/0509 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 22, 2010
From: NANOCONDUCTION, INC.
To: UNIDYM, INC.
Reel/Frame 025390/0874 →
RELEASE OF SECURITY INTEREST Recorded Jul 9, 2010
From: UNIDYM, INC.
To: VENTURE LENDING & LEASING IV, INC.
Reel/Frame 024651/0633 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2006
From: DANGELO, CARLOS; PADMAKUMAR, BALA
To: NANOCONDUCTION, INC.
Reel/Frame 018226/0174 →