Flash ADC with sparse codes matched to input noise
View Patent ↗An analog-to-digital converter (ADC) architecture to implement a non-linear flash ADC. The apparatus includes a non-linear resistor, a non-linear comparator, and an inverse non-linear encoder. The non-linear resistor has an input and a plurality of non-linear voltage outputs. The non-linear comparator ladder is coupled to the plurality of non-linear voltage outputs of the non-linear resistor. The non-linear comparator ladder includes a bank of comparators to compare an input signal to each of a plurality of non-linear voltage signals corresponding to the plurality of non-linear voltage outputs. The inverse non-linear encoder is coupled to the non-linear comparator ladder. The inverse non-linear encoder generates a digital output code based on the input signal and the plurality of non-linear voltage signals.
1. An apparatus, comprising:
a non-linear resistance ladder having an input and a plurality of non-linear voltage outputs, the non-linear resistance ladder having a single discrete geometry with multiple portions of distinct resistance;
a non-linear comparator ladder coupled to the plurality of non-linear voltage outputs of the non-linear resistance ladder, wherein the non-linear comparator ladder comprises a bank of comparators to compare an input signal to each of a plurality of non-linear voltage signals corresponding to the plurality of non-linear voltage outputs; and
an inverse non-linear encoder coupled to the non-linear comparator ladder to generate a digital output code based on the input signal and the plurality of non-linear voltage signals.
2. The apparatus of claim 1 , wherein the inverse non-linear encoder comprises a binary encoder.
3. The apparatus of claim 1 , wherein the inverse non-linear encoder comprises a Gray code encoder and a Gray-to-binary code converter.
4. The apparatus of claim 1 , further comprising first and second voltage inputs coupled to the non-linear resistance ladder to generate the plurality of non-linear voltage signals, wherein the input signal comprises an image sensor readout voltage, and a plurality of comparator output signals comprise a non-linear thermometer code.
5. The apparatus of claim 4 , wherein the digital output signal of the inverse non-linear encoder comprises a digital representation of the non-linear thermometer code.
6. The apparatus of claim 1 , further comprising a bank of preamplifiers coupled between the non-linear resistor and the non-linear comparator ladder.
7. The apparatus of claim 6 , wherein the bank of comparators, the bank of preamplifiers, and the inverse non-linear encoder share a common clock signal.
8. The apparatus of claim 1 , wherein the apparatus comprises an analog-to-digital converter flash architecture.
9. An apparatus, comprising:
a non-linear resistance ladder having an input and a plurality of non-linear voltage outputs;
a non-linear comparator ladder coupled to the plurality of non-linear voltage outputs of the non-linear resistance ladder, wherein the non-linear comparator ladder comprises a bank of comparators to compare an input signal to each of a plurality of non-linear voltage signals corresponding to the plurality of non-linear voltage outputs; and
an inverse non-linear encoder coupled to the non-linear comparator ladder to generate a digital output code based on the input signal and the plurality of non-linear voltage signals, wherein a code density of the digital output code is approximately matched to noise properties of the input signal, the noise properties characterizing a low noise amplitude associated with a dark part of an image and a high noise amplitude associated with a light part of the image.
10. An apparatus, comprising:
a non-linear resistance ladder having an input and a plurality of non-linear voltage outputs;
a non-linear comparator ladder coupled to the plurality of non-linear voltage outputs of the non-linear resistance ladder, wherein the non-linear comparator ladder comprises a bank of comparators to compare an input signal to each of a plurality of non-linear voltage signals corresponding to the plurality of non-linear voltage outputs;
an inverse non-linear encoder coupled to the non-linear comparator ladder to generate a digital output code based on the input signal and the plurality of non-linear voltage signals;
a bank of preamplifiers coupled between the non-linear resistor and the non-linear comparator ladder, wherein the bank of comparators, the bank of preamplifiers, and the inverse non-linear encoder share a common clock signal; and
an error correction block coupled between the non-linear comparator ladder and the inverse non-linear encoder.
11. The apparatus of claim 10 , further comprising:
a reference buffer coupled to the non-linear comparator ladder; and
a bias voltage source coupled to the bank of preamplifiers and the non-linear comparator ladder.
12. A method, comprising:
receiving an input signal associated with an image sensor readout;
comparing the input signal with each of a plurality of non-linear voltage signals;
generating a digital output code based on the input signal and the plurality of non-linear voltage signals; and
generating the plurality of non-linear voltage signals from a non-linear resistance ladder, wherein the plurality of non-linear voltage signals comprise a dithered subset of a plurality of linear voltage steps equally distributed over a voltage range.
13. The method of claim 12 , further comprising generating a non-linear thermometer code based on the comparison of the input signal with each of the plurality of non-linear voltage signals.
14. The method of claim 12 , wherein a voltage difference between consecutive voltage signals of the plurality of non-linear voltage signals is greater than a noise component of the input signal.