Circuit and method for retrieving data stored in semiconductor memory cells
View Patent ↗A circuit comprises at least one memory cell adapted to store data in terms of values of an electrical characteristic thereof, which exhibits a variability with temperature according to a first variation law; a voltage generator is provided for generating a voltage to be supplied to the at least one memory cell for retrieving the data stored therein, the voltage generator including first means adapted to cause the generated voltage take a value in a set of target values including at least one target value, corresponding to an operation to be performed on the memory cell. The voltage generator comprises second means for causing the value taken by the generated voltage vary with temperature according to a prescribed second variation law exploiting a compensation circuit element having said electrical characteristic.
1. A voltage generation circuit for developing a plurality of read voltages and a plurality of program verify voltages to be applied to nonvolatile memory cells, each of the memory cells having an associated threshold voltage that is a function of temperature, the voltage generation circuit comprising:
a voltage regulator circuit that receives an enable signal and operable to develop a plurality of internal voltages, each of the internal voltages having a value that is substantially independent of temperature, and the voltage regulator circuit further operable to output a selected one of the internal voltages as a regulated output voltage in response to the enable signal;
a compensation voltage generator coupled to the voltage regulator circuit to receive one of the internal voltages, the compensation voltage generator having a compensation threshold voltage having the same function of temperature as threshold voltages of the memory cells, and the compensation voltage generator operable to develop a compensation voltage from the internal voltage and the compensation threshold voltage; and
a voltage combining circuit coupled to the voltage regulator circuit and the compensation voltage generator, the combining circuit operable to combine the regulated output voltage and the compensation voltage to generate a corresponding read voltage or program verify voltage.
2. The voltage generation circuit of claim 1 wherein the voltage regulator circuit comprises a voltage divider formed by a plurality of resistors connected in series between a supply voltage and a reference voltage, and the internal voltages are developed at nodes of the series connected resistors.
3. The voltage generation circuit of claim 1 wherein the voltage regulator circuit further comprises a band gap reference voltage generator that is operable to develop a band gap reference voltage that the voltage regulator circuit utilizes in generating the internal voltages.
4. The voltage generation circuit of claim 1 wherein the compensation voltage generator comprises:
a MOS transistor having a gate that receives the internal voltage from the voltage regulator circuit, a drain adapted to receive a supply voltage, and a source, the threshold voltage of the transistor corresponding to the compensation threshold voltage; and
a resistor coupled between the source of the transistor and a reference voltage source; and
a buffer having an input coupled to the source of the transistor an operable to develop the compensation voltage on an output, with the compensation voltage having a value corresponding to a voltage across the resistor.
5. The voltage generation circuit of claim 4 wherein the voltage combining circuit comprises:
an operational amplifier having a non-inverting input coupled to receive the regulated output voltage, an inverting input, and an output;
two series connected resistors coupled between the output of the buffer and the output of the operational amplifier, with a node formed at the interconnection of the two resistors being connected to the inverting input of the operational amplifier.
6. The voltage generation circuit of claim 5 wherein the voltage combining circuit is operable to combine the regulated output voltage and the compensation to generate the corresponding read voltage or program verify voltage having a variation as a function of temperature that is proportional to a variation as a function of temperature of the threshold voltages of the memory cells.
7. A memory device, comprising:
an array of nonvolatile memory cells, each of the memory cells having an associated threshold voltage that varies as a function of temperature;
address circuitry coupled to the array and being operable to access selected memory cells in the array responsive to a memory address;
read/write circuitry coupled to the array and operable to program and read data from memory cells in the array, the read/write circuitry including a voltage generation circuit operable to develop a plurality of read voltages and a plurality of program verify voltages that are applied to accessed memory cells in the array, the voltage generation circuit comprising:
a voltage regulator circuit that receives an enable signal and operable to develop a plurality of internal voltages, each of the internal voltages having a value that is substantially independent of temperature, and the voltage regulator circuit further operable to output a selected one of the internal voltages as a regulated output voltage in response to the enable signal;
a compensation voltage generator coupled to the voltage regulator circuit to receive one of the internal voltages, the compensation voltage generator having a compensation threshold voltage having the same function of temperature as threshold voltages of the memory cells, and the compensation voltage generator operable to develop a compensation voltage from the internal voltage and the compensation threshold voltage; and
a voltage combining circuit coupled to the voltage regulator circuit and the compensation voltage generator, the combining circuit operable to combine the regulated output voltage and the compensation voltage to generate a corresponding read voltage or program verify voltage; and
control circuitry coupled to the address circuitry and read/write circuitry and operable to apply a plurality control signals to the address circuitry and read/write circuitry to control the overall operation of the memory device.
8. The memory device of claim 7 wherein the array of memory cells comprises an array of multilevel memory cells.
9. The memory device of claim 7 wherein each of the memory cells comprises a FLASH memory cell.
10. The memory device of claim 9 wherein the array of memory cells has a NAND architecture.
11. A method for developing a plurality of read voltages and a plurality of program verify voltages to be applied to nonvolatile memory cells, each of the memory cells having a threshold voltage that varies as a function of temperature, the method comprising:
generating a plurality of internal voltages, each of the internal voltages having a value that is substantially independent of temperature;
selecting one of the internal voltages as a regulated output voltage;
generating a compensation voltage from one of the internal voltages, the compensation voltage having a value that varies as a function of temperature, with the variation being proportional to the variation of the threshold voltages of the memory cells; and
combining the regulated output voltage and the compensation voltage to generate a corresponding read voltage or program verify voltage.
12. The method of claim 11 wherein each of the memory cells includes a transistor and wherein generating the compensation voltage includes a threshold voltage of a transistor that is the same as the transistors in the memory cells.
13. The method of claim 11 wherein generating a plurality of internal voltages includes using a band-gap reference voltage in generating the internal voltages.
14. The method of claim 13 wherein the internal voltages are developed on a plurality of nodes and wherein selecting one of the internal voltages as a regulated output voltage comprises coupling a selected one of the nodes to an output node.