IP Library Granted Patent US 7,611,955
Granted Patent B2
US 7,611,955 · App. 11/454,403 · Granted Nov 3, 2009

Method of forming a bipolar transistor and semiconductor component thereof

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Quick Facts
Patent No.
US 7,611,955
App. No.
11/454,403
Granted
Nov 3, 2009
Kind
B2
Abstract

A semiconductor component is formed using the following processes: (a) forming a first dielectric layer over the semiconductor substrate; (b) forming a base electrode for the bipolar transistor over the dielectric layer; (c) forming an oxide nitride structure over the base electrode; (d) forming a first spacer adjacent to the oxide nitride structure and the base electrode; (e) removing a top layer of the oxide nitride structure; (f) removing a first portion of the dielectric layer; (g) forming an epitaxial layer over the semiconductor substrate; (h) forming a second spacer over the epitaxial layer; and (i) forming an emitter electrode over the epitaxial layer and adjacent to the second spacer.

Claims (104)

1. A method of forming a bipolar transistor comprising:

forming a first dielectric layer over a semiconductor substrate;

forming a base electrode for the bipolar transistor over the first dielectric layer;

forming an oxide nitride structure over the base electrode;

forming a first spacer adjacent to the oxide nitride structure and the base electrode;

removing a top layer of the oxide nitride structure;

removing a first portion of the first dielectric layer;

forming an epitaxial layer over the semiconductor substrate;

forming a second spacer over the epitaxial layer;

forming an emitter electrode adjacent over the epitaxial layer and adjacent to the second spacer;

forming a third spacer adjacent to the oxide nitride structure before forming the first spacer; and

removing the third spacer,

wherein:

removing the third spacer, removing the top layer of the oxide nitride structure, and removing a first portion of the first dielectric layer occur simultaneously with each other and occur after forming the first spacer.

2. The method of claim 1 , wherein:

forming the epitaxial layer comprises:

forming the epitaxial layer with a portion of the epitaxial layer formed underneath the base electrode and the first spacer.

3. The method of claim 1 , wherein:

removing the first portion of the first dielectric layer comprises:

exposing a portion of the semiconductor substrate; and

forming the epitaxial layer comprises:

forming the epitaxial layer over the portion of the semiconductor substrate.

4. The method of claim 1 , wherein:

forming the epitaxial layer comprises:

forming the epitaxial layer with a thickness less than a thickness of the first dielectric layer.

5. The method of claim 1 , wherein:

forming the second spacer comprises:

forming a second spacer adjacent to the first spacer, such that the first spacer is located between the second spacer and the oxide nitride structure.

6. The method of claim 1 , wherein:

forming the second spacer comprises:

forming the second spacer over a portion of the epitaxial layer and under the first spacer.

7. The method of claim 6 , wherein:

forming the second spacer comprises:

forming an oxide layer over the epitaxial layer, the first spacer and the oxide nitride structure; and

anisotropically etching the oxide layer to form the second spacer.

8. The method of claim 1 , wherein:

forming the first spacer comprises:

forming a nitride layer over the first dielectric layer and the oxide nitride structure; and

anisotropically etching the nitride layer to form the first spacer.

9. The method of claim 1 , further comprising:

providing a substrate comprising silicon for the semiconductor substrate, and

wherein:

forming the epitaxial layer comprises:

forming a first silicon epitaxial layer over a portion of the silicon substrate;

forming a SiGeC epitaxial layer over the first silicon layer; and

forming a second silicon epitaxial layer over the SiGeC epitaxial layer.

10. A semiconductor component formed from the method of claim 1 .

11. The method of claim 1 , wherein:

forming the oxide nitride structure over the base electrode comprises:

forming a first oxide layer over the base electrode;

forming a first nitride layer over the first oxide layer; and

forming a second oxide layer over the first nitride layer.

12. A method of forming a bipolar transistor comprising:

forming a first dielectric layer over a semiconductor substrate;

forming a base electrode for the bipolar transistor over the first dielectric layer;

forming an oxide nitride structure over the base electrode;

forming a second dielectric layer over the oxide nitride structure and the first dielectric layer;

anisotropically etching a portion of the second dielectric layer to form a first spacer adjacent to the base electrode and the oxide nitride structure;

removing a top layer of the oxide nitride structure after anisotropically etching the portion of the second dielectric layer;

removing a first portion of the first dielectric layer to expose a portion of the semiconductor substrate;

growing an epitaxial layer over the portion of the silicon substrate;

forming a second spacer over the epitaxial layer;

forming an emitter electrode aver the apitaxial to the first spacer and the second spacer;

forming a third spacer adjacent to the oxide nitride structure before forming the second dielectric layer; and

removing the third spacer,

wherein:

removing the third spacer, removing the top layer of the oxide nitride structure, and removing the first portion of the first dielectric layer occur simultaneously with each other.

13. The method of claim 12 , further comprising:

using the third spacer as an etch mask while anisotropically etching the portion of the second dielectric layer.

14. The method of claim 12 , wherein:

forming the second spacer comprises:

forming the second spacer over a portion of the epitaxial layer and under the first spacer.

15. The method of claim 12 , wherein:

forming the epitaxial layer comprises:

forming the epitaxial layer with a thickness less than a thickness of the first dielectric layer.

16. A semiconductor component formed from the method of claim 12 .

17. The method of claim 12 , further comprising:

forming a second oxide layer over the base electrode before forming the first oxide laser and the first nitride layer,

wherein:

forming a first nitride layer over the base electrode comprises:

forming a first nitride layer over the second oxide layer.

18. A method of forming a bipolar transistor comprising:

forming a first dielectric layer over a semiconductor substrate;

forming a base electrode for the bipolar transistor over the first dielectric layer;

forming a first oxide layer over the base electrode;

forming a first nitride layer over the first oxide layer;

forming a second oxide layer over the first nitride layer, wherein the first oxide lever, the first nitride layer, and the second oxide layer form an oxide nitride structure;

forming a first spacer adjacent to the oxide nitride structure and the base electrode;

removing the second oxide layer;

removing a first portion of the first dielectric layer;

forming an epitaxial layer over the semiconductor substrate;

forming second spacer over a portion of the epitaxial layer and adjacent to the second spacer; and

removing the third spacer,

wherein:

removing the third spacer, removing the second oxide layer, and removing a first portion of the first dielectric layer occur simultaneously with each other and occur after forming the first spacer.

19. The method of claim 18 wherein:

forming the first spacer comprises:

forming a nitride layer over the first dielectric layer and the oxide nitride structure; and

anisotropically etching the nitride layer to form the first spacer.

20. The method of claim 18 , wherein:

removing the first portion of the first dielectric layer comprises:

exposing a portion of the semiconductor substrate; and

forming the epitaxial layer comprises:

forming the epitaxial layer over the portion of the semiconductor substrate.

Assignments (32)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
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From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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