Memory pipelining in an integrated circuit memory device using shared word lines
A method for pipelining a memory in an integrated circuit includes providing a first clock phase and providing a second clock phase, wherein the first clock phase and the second clock phase are at least partially non-overlapping. The method further includes providing a first memory array and providing a second memory array, wherein the second memory array shares a wordline with the first memory array. The method further includes using said wordline to select at least one row of the first memory array during the first clock phase. The method further includes using said wordline to select at least one row of the second memory array during the second clock phase.
1. A method for pipelining a memory in an integrated circuit, comprising:
providing a first clock phase;
providing a second clock phase, wherein the first clock phase and the second clock phase are at least partially non-overlapping;
providing a first memory array;
providing a second memory array, wherein the second memory array shares a wordline with the first memory array;
using said wordline to select at least one row of the first memory array during the first clock phase; and
using said wordline to select at least one row of the second memory array during the second clock phase.
2. A method as in claim 1 , wherein the first clock phase and the second clock phase are at least ninety percent non-overlapping.
3. A method as in claim 1 , wherein the first clock phase comprises a high phase of a clock signal and the second clock phase comprises a low phase of said clock signal.
4. A method as in claim 1 , wherein the first clock phase and the second clock phase are provided by different clock signals.
5. A method as in claim 1 , further comprising:
decoding an address to provide a decoded address;
using the decoded address to select said wordline to read the first memory array during the first clock phase; and
using the decoded address to again select said wordline to read the second memory array during the second clock phase.
6. A method as in claim 1 , further comprising:
latching the wordline to store a wordline value; and
using the wordline value to drive the wordline during reading of the second memory array.
7. A method as in claim 1 , wherein a transition of the wordline arrives at latching circuitry before, concurrent with, or after a first edge of the second clock phase.
8. A method as in claim 1 , wherein the memory comprises a cache tag portion.
9. A method as in claim 8 , wherein the cache tag portion is greater than sixteen bits.
10. A method as in claim 8 , wherein the cache tag portion operates at a frequency greater than two gigahertz.
11. A method as in claim 1 , further comprising:
providing a third clock phase;
providing a third memory array, wherein the third memory array shares the wordline with the first memory array and the second memory array; and
using said wordline to select at least one row of the third memory array during the third clock phase.
12. A method as in claim 1 , wherein the first memory array and the second memory array are pitch matched in a direction of the wordline.
13. An integrated circuit having a pipelined cache, the pipelined cache comprising:
An information array having a plurality of ways;
a tag array having a first tag portion and a second tag portion, wherein the first tag portion is accessed during a first clock phase, and wherein the second tag portion is accessed during a second clock phase, wherein the first clock phase and the second clock phase are at least partially non-overlapping; and
compare circuitry coupled to said tag array and said information array.
14. An integrated circuit as in claim 13 , wherein said compare circuitry compares a first portion of a received address with an output of the first tag portion during the first clock phase to determine a speculative way select for the information array, and which compares a second portion of the received address with an output of the second tag portion during the second clock phase to determine validity of the speculative way select for the information array.
15. An integrated circuit as in claim 13 , wherein the first tag portion and the second tag portion share a wordline, wherein the pipelined cache further comprises latching circuitry which stores the wordline from the first tag portion, and wherein said latching circuitry drives said wordline in the second tag portion.
16. An integrated circuit as in claim 15 , wherein a transition of the wordline arrives at the latching circuitry before, concurrent with, or after a first edge of the second clock phase.
17. A method as in claim 13 , wherein the pipelined cache operates at a frequency greater than two gigahertz.
18. A method for pipelining a memory in an integrated circuit, the method comprising:
providing a first clock phase;
providing a second clock phase, wherein the first clock phase and the second clock phase are at least partially non-overlapping;
providing a first memory array;
providing a second memory array, wherein the first memory array and the second memory array share a first wordline;
providing a third memory array;
providing a fourth memory array, wherein the third memory array and the fourth memory array share a second wordline;
using said first wordline to select at least one row of the first memory array and provide a first output during the first clock phase;
using said second wordline to select at least one row of the third memory array and provide a third output during the first clock phase;
receiving a select signal;
using the select signal to select one of the first output and the third output; and
using the select signal to determine whether to select the at least one row of the second memory array or at least one row of the fourth memory array during the second clock phase.
19. A method as in claim 18 , wherein the select signal represents a least significant bit of an address.
20. A method as in claim 18 , wherein the select signal is stored.