Leaded stacked packages having integrated upper lead

1. A semiconductor package comprising:

a leadframe;

an upper lead disposed above the leadframe;

a first die attached to a lower surface of the upper lead to provide electrical conductivity from the first die to the upper lead;

a second die attached to the first die; and

a removable elevated die paddle disposed above the upper lead and second die to temporarily support the first and second dies within the semiconductor package during manufacturing.

2. The semiconductor package of claim 1 , wherein the removable elevated die paddle is removed using a grind wheel.

3. The semiconductor package of claim 1 , wherein a surface of the upper lead is adapted to provide electrical conductivity to a second semiconductor package configured in a package-on-package (PoP) arrangement.

4. The semiconductor package of claim 3 , wherein the second semiconductor package further comprises a leaded package, array package, flip chip die, or a passive component.

5. A semiconductor package comprising:

a leadframe;

an upper lead and elevated die paddle assembly disposed above the leadframe, wherein a portion of the upper lead and elevated die paddle assembly is removed to provide electrical conductivity to a second semiconductor package;

a first die connected a lower surface of the upper lead and elevated die paddle assembly to support the first die within the semiconductor package;

a second die connected to the first die; and

an encapsulant formed over a portion of the second die and upper lead for providing structural support to the first and second die within the semiconductor package.

6. The semiconductor package of claim 5 , wherein the second die further includes a land grid array (LGA) or Quad Flat Nonleaded (QFN) package.

7. The semiconductor package of claim 5 , wherein the second semiconductor package is adapted for a package-on-package (PoP) arrangement.

8. The semiconductor package of claim 7 , wherein the second semiconductor package further comprises a leaded package, array package, flip chip die, or a passive component.

9. A method of manufacturing a semiconductor package comprising:

providing a leadframe having an upper lead, a lower lead, and a elevated die paddle;

attaching a first die to a second die, the first die attached to a plurality of dies in a wafer form;

singulating the first die from the plurality of dies; and

attaching the first and second dies to the elevated die paddle structure;

wire bonding the first die to the lower lead;

forming an encapsulant over a portion of the first and second dies; and

removing the elevated die paddle to expose a surface of the upper lead and second die.

10. The method of manufacturing of claim 9 , wherein removing the elevated die paddle is performed using a grinding process.

11. The method of manufacturing of claim 10 , wherein the grinding process further includes wheel grinding, chemical etching or a chemical mechanical polishing (CMP) process.

12. The method of manufacturing of claim 9 , wherein the first die is attached to the second die using a ball grid array (BGA).

13. The method of manufacturing of claim 9 , wherein a surface of the upper lead is adapted to provide electrical conductivity to a second semiconductor package configured in a package-on-package (PoP) arrangement.

14. The method of manufacturing of claim 13 , wherein the second semiconductor package further comprises a leaded package, array package, flip chip die, or a passive component.