IP Library Granted Patent US 8,081,006
Granted Patent B2
US 8,081,006 · App. 11/460,948 · Granted Dec 20, 2011

Non-linear sensor temperature compensation using summed temperature compensation signals

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Quick Facts
Patent No.
US 8,081,006
App. No.
11/460,948
Granted
Dec 20, 2011
Kind
B2
Abstract

A sensor temperature compensation circuit that includes a sensor and non-linear temperature compensation circuit that compensates for non-linear temperature dependencies in offset and/or gain generated by the sensor. For instance, to at least partially compensate for offset temperature dependencies, a summer adds two offset compensation signals, the ratio of the second to the first being a function of temperature. The summed signal may then be multiplied by a function of temperature. The summed signal may then be used to provide the non-linear temperature compensation to the offset. Alternatively or in addition, to at least partially compensate for gain temperature dependencies, a summer adds two gain compensation signals, the ratio of the second to the first being a function of temperature. The summed signal may then be multiplied by a function of temperature. The summed signal may then be used to provide non-linear temperature compensation to the gain.

Claims (30)

1. A sensor temperature compensation circuit comprising:

a sensor that is structured such that when the sensor is operating, the sensor senses a physical parameter and generates an electrical sensor output signal representing the physical parameter;

an offset temperature compensation circuit that receives the electrical sensor output signal directly from the sensor, and is a non-linear offset temperature compensation circuit comprising:

a first amplifier that receives the electrical sensor output signal and generates an amplified electrical sensor output signal;

a first summer that receives the amplified electrical sensor output signal as a first input, a second input from an offset digital-to-analog converter (DAC), and a third input from a first temperature DAC and sums the first, second, and third inputs to generate a non-linear offset temperature compensation circuit output that is provided to a non-linear gain temperature compensation circuit;

the offset DAC that generates the second input to the first summer by multiplying a voltage offset and a reference value of the sensor;

the first temperature DAC that generates the third input to the first summer by multiplying a summed signal received from a second summer with the sensor temperature, the third input to the first summer for performing linear sensor temperature compensation on an offset characteristic of the electrical sensor output signal;

the second summer that receives a first input from an OTC DAC and a second input from a first temperature function DAC and sums the first and second inputs to generate the summed signal that is provided to the first temperature DAC;

the OTC DAC that generates the first input to the second summer by multiplying an offset temperature coefficient (OTC) with the reference value of the sensor; and

the first temperature function DAC that generates the second input to the second summer by multiplying an offset parameter that is a function of the sensor temperature with the reference value of the sensor, the generated second input to the second summer for performing non-linear sensor temperature compensation on an offset characteristic of the electrical sensor output signal; and

a non-linear gain temperature compensation circuit comprising:

a variable gain amplifier that amplifies the non-linear offset temperature compensation circuit output to generate a variable gain amplifier output signal;

a third amplifier, a GTC DAC, and a second temperature function DAC, wherein each of the third amplifier, the GTC DAC, and the second temp function DAC receive the variable gain amplifier output signal,

wherein the third amplifier amplifies the variable gain amplifier output signal to generate a first input to a third summer;

wherein the GTC DAC multiplies the variable gain amplifier output signal with a gain temperature coefficient (GTC) to generate a first input to a fourth summer, the first input for performing linear sensor temperature compensation on a gain characteristic of the electrical sensor output signal; and

wherein the second temperature function DAC multiples the variable gain amplifier output signal with a gain parameter that is a function of the sensor temperature to generate a second input to the fourth summer, the second input for performing non-linear sensor temperature compensation on a gain characteristic of the electrical sensor output signal;

the fourth summer that receives the first and second inputs to the fourth summer and generates a summed signal as an input to a second temperature DAC;

the fourth temperature DAC that multiplies the summed signal with the sensor temperature to generate a second input to the third summer; and

the third summer that sums the first and second inputs to the third summer to generate the output of the non-linear gain temperature compensation circuit.

2. A sensor temperature compensation circuit in accordance with claim 1 , wherein the gain parameter that is a function of the sensor temperature is a constant multiplier if the sensor temperature is on a first side of a reference temperature, and is a stepped multiplier if the sensor temperature is on a second side of the reference temperature.

3. A sensor temperature compensation circuit in accordance with claim 2 , wherein the sensor temperature is a digital temperature value representation of the current temperature of the sensor, and wherein at least the most significant bit of the digital temperature value is used to identify which side of the reference temperature the sensor temperature is.

4. A sensor temperature compensation circuit in accordance with claim 3 , wherein one or more of the other bits of the digital temperature value are used to define step boundaries of the stepped multiplier if the sensor temperature is on the second side of the reference temperature.

5. A sensor temperature compensation circuit in accordance with claim 2 , wherein the first side of the reference temperature is below the reference temperature, and the second side of the reference temperature is above the reference temperature.

6. A sensor temperature compensation circuit in accordance with claim 2 , wherein the first side of the reference temperature is above the reference temperature, and the second side of the reference temperature is below the reference temperature.

7. A sensor temperature compensation circuit in accordance with claim 1 , wherein the non-linear gain compensation circuit further comprises:

a fourth amplifier that amplifies the output of the third summer.

8. A sensor temperature compensation circuit in accordance with claim 1 , wherein the offset parameter that is a function of the sensor temperature is a constant multiplier if the sensor temperature is on a first side of a reference temperature, and is a stepped multiplier if the sensor temperature is on a second side of the reference temperature.

9. A sensor temperature compensation circuit in accordance with claim 8 , wherein the sensor temperature is a digital temperature value representation of the current temperature of the sensor, and wherein at least the most significant bit of the digital temperature value is used to identify which side of the reference temperature the sensor temperature is.

10. A sensor temperature compensation circuit in accordance with claim 9 , wherein one or more of the other bits of the digital temperature value are used to define step boundaries of the stepped multiplier if the sensor temperature is on the second side of the reference temperature.

11. A sensor temperature compensation circuit in accordance with claim 8 , wherein the first side of the reference temperature is below the reference temperature, and the second side of the reference temperature is above the reference temperature.

Assignments (8)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT AND COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038631/0345 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A. (ON ITS BEHALF AND ON BEHALF OF ITS PREDECESSOR IN INTEREST, CHASE MANHATTAN BANK)
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038632/0074 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
BILL OF SALE Recorded May 17, 2010
From: AMI SEMICONDUCTOR, INC.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 024390/0404 →
SECURITY AGREEMENT Recorded Jun 23, 2008
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; AMIS HOLDINGS, INC.; AMI SEMICONDUCTOR, INC.; AMIS FOREIGN HOLDINGS INC.; AMI ACQUISITION LLC
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 021138/0070 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 13, 2006
From: TSUCHIYA, MUNENORI; PIQUET, LUCAS LAREN; PETERSEN, LARRY
To: AMI SEMICONDUCTOR, INC.
Reel/Frame 018629/0893 →