IP Library Granted Patent US 7,936,055
Granted Patent B2
US 7,936,055 · App. 11/466,748 · Granted May 3, 2011

Integrated circuit package system with interlock

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Quick Facts
Patent No.
US 7,936,055
App. No.
11/466,748
Granted
May 3, 2011
Kind
B2
Abstract

An integrated circuit package system is provided including forming a first external interconnect and a die paddle having a slot, forming an inner terminal from a peripheral region of the die paddle, connecting an integrated circuit die and the peripheral region for ground connection, and molding through the slot.

Claims (45)

1. A method of manufacturing an integrated circuit package system comprising:

forming a first external interconnect and a die paddle having a slot;

forming inner terminals by removal of portions of a peripheral region so that the inner terminals extend from recessed portions of a bottom surface of the peripheral region and separated from the die paddle by the slot;

connecting an integrated circuit die and the peripheral region for ground connection; and

molding an encapsulation through the slot adjacent to the inner terminal and completely under the peripheral region including exposing the inner terminal through the encapsulation.

2. The method as claimed in claim 1 wherein:

forming the first external interconnect has an outer terminal; and

molding through the slot covers the integrated circuit die, the first external interconnect with the outer terminal exposed, and the die paddle with the inner terminal exposed.

3. The method as claimed in claim 1 wherein connecting the integrated circuit die includes connecting the integrated circuit die and the first external interconnect.

4. The method as claimed in claim 1 further comprising forming a second external interconnect, having a second finger end, adjacent to the first external interconnect having a first finger end, wherein the widths of the first finger end and the second finger end are complementary.

5. The method as claimed in claim 1 further comprising forming outer terminals having an outer separation between the outer terminals different from an inner separation between inner terminals.

6. A method of manufacturing an integrated circuit package system comprising:

forming a first external interconnect, a die paddle having a slot, and a tie bar connected to the die paddle;

forming an outer terminal from the first external interconnect;

forming inner terminals by removal of portions of a peripheral region so that the inner terminals extend from recessed portions of a bottom surface of the peripheral region and separated from the die paddle by the slot;

connecting an integrated circuit die and the peripheral region for ground connection; and

molding an encapsulation through the slot adjacent to the inner terminal and completely under the peripheral region with the outer terminal and the inner terminal exposed.

7. The method as claimed in claim 6 further comprising forming a plating on the peripheral region.

8. The method as claimed in claim 6 wherein the molding includes covering a first finger end of the first external interconnect and the tie bar.

9. The method as claimed in claim 6 wherein forming the die paddle includes forming an electromagnetic interference shield and a heat spreader.

10. The method as claimed in claim 6 further comprising forming an electronic system having the integrated circuit package system.

11. An integrated circuit package system comprising:

a first external interconnect;

a die paddle having a slot;

inner terminals extend from recessed portions of a bottom surface of a peripheral region separated from the die paddle by the slot;

an integrated circuit die;

an internal interconnect between the integrated circuit die and the peripheral region for ground connection; and

an encapsulation through the slot adjacent to the inner terminal and completely under the peripheral region includes the inner terminals exposed from the encapsulation.

12. The system as claimed in claim 11 wherein:

the first external interconnect has an outer terminal; and

the encapsulation through the slot is a cover for the integrated circuit die, the first external interconnect with the outer terminal exposed, and the die paddle with the inner terminal exposed.

13. The system as claimed in claim 11 further comprising a second internal interconnect between the integrated circuit die and the first external interconnect.

14. The system as claimed in claim 11 further comprising a second external interconnect, having a second finger end, adjacent to the first external interconnect having a first finger end, wherein the widths of the first finger end and the second finger end are complementary.

15. The system as claimed in claim 11 further comprising outer terminals having an outer separation between the outer terminals different from an inner separation between inner terminals.

16. The system as claimed in claim 11 wherein:

the first external interconnect has an outer terminal;

the die paddle having the slot is connected to a tie bar;

the inner terminal of the peripheral region of the die paddle is for ground connection;

the integrated circuit die is over the die paddle;

the internal interconnect between the integrated circuit die and the peripheral region for ground connection is a bond wire; and

the encapsulation through the slot has the outer terminal and the inner terminal exposed.

17. The system as claimed in claim 16 further comprising a plating on the peripheral region.

18. The system as claimed in claim 16 wherein the encapsulation is a cover for a first finger end of the first external interconnect and the tie bar.

19. The system as claimed in claim 16 wherein the die paddle is an electromagnetic interference shield and a heat spreader.

20. The system as claimed in claim 16 further comprising an electronic system having the integrated circuit package system.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON COVER SHEET FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. PREVIOUSLY RECORDED ON REEL 064783 FRAME 0896. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECTIVE CHANGE OF NAME. Recorded Sep 22, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065015/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON COVERSHEET FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. PREVIOUSLY RECORDED ON REEL 038378 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Sep 14, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064962/0123 →
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. (REEL: 038378 FRAME: 0292) Recorded Aug 30, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE.LTE.
Reel/Frame 064783/0896 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052907/0650 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0292 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 23, 2006
From: DIMAANO, JR., ANTONIO B.; MARIMUTHU, PANDI CHELVAM
To: STATS CHIPPAC LTD.
Reel/Frame 018162/0422 →