Method to improve performance of a bipolar device using an amorphizing implant
View Patent ↗The invention, in one aspect, provides a semiconductor device that comprises a bipolar transistor located over and within a semiconductor substrate, a collector located within a tub of the bipolar transistor and having an amorphous region formed at least partially therein, a base located over the collector, and an emitter located over the base. There is also provided a method of fabricating the semiconductor device.
1. A method of manufacturing a semiconductor device, comprising:
forming an amorphous region at least partially in a collector region for a bipolar transistor;
forming a collector in the collector region;
forming a base over the collector region; and
forming an emitter over the base.
2. The method recited in claim 1 , wherein the amorphous region is formed by implanting a dopant having an atomic weight greater than boron.
3. The method recited in claim 2 , wherein the dopant is silicon, germanium, argon, or neon.
4. The method recited in claim 2 , wherein implanting includes implanting silicon at a power ranging from about 400 keV to about 1000 keV and at a dosage concentration ranging from about 5 E13 atoms/cm 2 to about 5 E15 atoms/cm 2 .
5. The method recited in claim 1 , wherein forming the amorphous region and forming the collector occur concurrently.
6. The method recited in claim 5 , wherein forming the amorphous region and forming the collector comprises implanting boron, aluminum, gallium, or indium.
7. The method recited in claim 6 , wherein implanting comprises implanting with boron wherein a wafer substrate temperature ranging from about 25° C. to about 50° C. and at a beam current ranging from about 1 mA to about 3 mA.
8. The method recited in claim 7 , wherein implanting comprises implanting with boron at a dose ranging from about 8 E13 atoms/cm 2 to about 6 E14 atoms/cm 2 and at a power ranging from about 200 keV to about 500 keV.
9. The method recited in claim 6 wherein implanting comprises implanting with aluminum, gallium, or indium at a dose ranging from about 6 E13 atoms/cm 2 to about 6 E14 atoms/cm 2 and at a power ranging from about 500 keV to about 3000 keV.
10. A method of manufacturing an integrated circuit, comprising:
forming non-bipolar transistors over a semiconductor substrate;
forming bipolar transistors over the semiconductor substrate, including forming an amorphous region at least partially in a collector region of at least one bipolar transistor;
forming a collector in the collector region; forming a base over the collector region; and forming an emitter over the base;
forming dielectric layers over the non-bipolar transistors and bipolar transistors; and
forming interconnects in the dielectric layers that electrically connect the non-bipolar and bipolar transistors.
11. The method recited in claim 10 , wherein the amorphous region is formed by implanting a dopant having an atomic weight greater than boron.
12. The method recited in claim 11 , wherein the dopant is silicon, germanium, argon, or neon.
13. The method recited in claim 11 , wherein implanting includes implanting silicon at a power ranging from about 400 keV to about 1000 keV and at a dosage concentration ranging from about 5 E13 atoms/cm 2 to about 5 E15 atoms/cm 2 .
14. The method recited in claim 10 , wherein forming the amorphous region and conducting occur concurrently.
15. The method recited in claim 14 , wherein forming the amorphous region and conducting comprises implanting boron, aluminum, gallium, or indium.
16. The method recited in claim 15 , wherein implanting comprises implanting with boron wherein a wafer substrate temperature ranges from about 25° C. to about 50° C. and at a beam current ranges from about 1 mA to about 3 mA.
17. The method recited in claim 16 , wherein implanting comprises implanting with boron at a dose ranging from about 8 E13 atoms/cm 2 to about 6 E14 atoms/cm 2 and at a power ranging from about 200 keV to about 500 keV.
18. The method recited in claim 15 wherein implanting comprises implanting with aluminum, gallium, or indium at a dose ranging from about 6E13 atoms/cm 2 to about 6E14 atoms/cm 2 and at a power ranging from about 500 keV to about 3000 keV.
19. A semiconductor device, comprising:
a bipolar transistor located over a semiconductor substrate;
a collector located within the semiconductor substrate and having an amorphous region formed at least partially therein;
a base located over the collector; and
an emitter located over the base.
20. The device recited in claim 19 , wherein the amorphous region includes implanted silicon.
21. The device recited in claim 19 , wherein the amorphous region includes aluminum, gallium, or indium.
22. The device recited in claim 19 , wherein a thickness of the amorphous region ranges from about 0.03 microns to about 1 micron and a depth of the amorphous region ranges from about 0.02 microns to about 1.8 microns.
23. The device recited in claim 19 , further comprising a plurality of bipolar transistors and non-bipolar transistors, dielectric layers located over the bipolar transistors and non-bipolar transistors; and interconnects formed within the dielectric layers that interconnect the bipolar transistors and non-bipolar transistors.