Non-volatile memory cell in standard CMOS process
View Patent ↗A non-volatile memory cell fabricated with a conventional CMOS process, including a flip-flop circuit having an NMOS transistor that shares a floating gate with a write PMOS capacitor and an erase PMOS capacitor. An erase function is implemented by inducing Fowler-Nordheim tunneling through the erase PMOS capacitor, thereby providing a positive charge on the floating gate. A write function is implemented by inducing Fowler-Nordheim tunneling through the NMOS transistor, thereby providing a negative charge on the floating gate. The write PMOS capacitor provides bias voltages during the erase and write operations. Prior to a read operation, the flip-flop circuit is reset. If the floating gate stores a positive charge, the NMOS transistor turns on, thereby switching the state of the flip-flop circuit. If the floating gate stores a negative charge, the NMOS transistor turns off, thereby leaving the flip-flop circuit in the reset state.
1. A non-volatile memory cell comprising:
a flip-flop circuit including a first MOS transistor having a first conductivity type, the first MOS transistor having a gate, a drain and a source, wherein the source is coupled to receive a write data value;
a first capacitor structure coupled to the gate of the first MOS transistor; and
a second capacitor structure coupled to the gate of the first MOS transistor, wherein the first MOS transistor, the first capacitor structure and the second capacitor structure share a common floating gate electrode.
2. The non-volatile memory cell of claim 1 , wherein the first capacitor structure comprises a MOS transistor having a second conductivity type, opposite the first conductivity type.
3. The non-volatile memory cell of claim 2 , wherein the second capacitor structure comprises a MOS transistor having the second conductivity type.
4. The non-volatile memory cell of claim 2 , wherein the second capacitor structure comprises a second gate electrode located over the floating gate electrode.
5. The non-volatile memory cell of claim 1 , wherein the second capacitor structure has an area at least 100 times greater than the first capacitor structure.
6. The non-volatile memory cell of claim 5 , wherein the second capacitor structure has an area at least 100 times greater than the area of the gate of the first MOS transistor.
7. The non-volatile memory cell of claim 1 , further comprising a second MOS transistor having the first conductivity type, wherein the second MOS transistor is configured to reset the flip-flop circuit during start-up of the non-volatile memory cell.
8. The non-volatile memory cell of claim 7 , further comprising a third MOS transistor having the first conductivity type, wherein the third MOS transistor is configured to isolate the first MOS transistor from the rest of the flip-flop circuit during start-up of the non-volatile memory cell.
9. The non-volatile memory cell of claim 1 , further comprising a current injection circuit coupled to the flip-flop circuit and forming a current mirror with the first MOS transistor, wherein the current injection circuit is configured to identify a read margin of the non-volatile memory cell.
10. A method of operating a non-volatile memory cell, comprising:
establishing a positive charge on a floating gate shared by a first MOS transistor having a first conductivity type, a first capacitor structure and a second capacitor structure, wherein the first MOS transistor is included in a flip-flop circuit, and wherein the positive charge is established by:
isolating the first MOS transistor from a plurality of other MOS transistors in the non-volatile memory cell;
coupling the first capacitor structure to a ground supply terminal; and
coupling the second capacitor structure to a positive voltage supply terminal, wherein electrons are removed from the floating gate by Fowler-Nordheim tunneling through the second capacitor structure.
11. The method of claim 10 , further comprising removing the positive charge previously established on the floating gate by:
isolating the first MOS transistor from the plurality of other MOS transistors in the non-volatile memory cell;
coupling the first and second capacitor structures to a positive voltage supply terminal; and
coupling the first MOS transistor to the ground supply terminal, wherein electrons are injected into the floating gate by Fowler-Nordheim tunneling through the first MOS transistor.
12. The method of claim 11 , further comprising reading the non-volatile memory cell by:
coupling the first MOS transistor to the plurality of other MOS transistors in the non-volatile memory cell; and
providing an output of the non-volatile memory cell in response to the charge on the floating gate.
13. The method of claim 12 , wherein the step of reading further comprises:
initially setting the output of the non-volatile memory cell; and
switching the output of the non-volatile memory cell only if the floating gate stores a positive charge.
14. The method of claim 10 , further comprising forming the first capacitor structure with a MOS transistor having a second conductivity type, opposite the first conductivity type.
15. The method of claim 11 , further comprising forming the second capacitor structure with a MOS transistor having the second conductivity type.
16. The method of claim 10 , further comprising selecting the area of the second capacitor structure to be at least 100 times greater than the area of the first capacitor structure.
17. The method of claim 16 , further comprising selecting the area of the second capacitor structure to be at least 100 times greater than a gate area of the first MOS transistor.
18. The method of claim 10 , further comprising a injecting current into the first MOS transistor to determine a read margin of the non-volatile memory cell.