Scalable electrically eraseable and programmable memory
View Patent ↗A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor, a second non-volatile memory transistor and a source access transistor. The source access transistor includes: a first source region continuous with a source region of the first non-volatile memory transistor; a second source region continuous with a source region of the second non-volatile memory transistor, and a drain region that extends downward through a first well region to contact a second well region. The first, second and third semiconductor regions and the second well region have a first conductivity type, and the first well region has a second conductivity type, opposite the first conductivity type.
1. A non-volatile memory array comprising:
one or more electrically erasable and programmable memory (EEPROM) cell pairs, each configured to store two data bits, and including:
a first non-volatile memory transistor having a first source region and a first drain region;
a second non-volatile memory transistor having a second source region and a second drain region, wherein the first source region, the first drain region, the second source region and the second drain region are separate regions having the same conductivity type; and
a source access transistor that shares the first source region with the first non-volatile memory transistor, and shares the second source region with the second non-volatile memory transistor.
2. The non-volatile memory array of claim 1 , further comprising a bit line coupled to the first drain region of the first non-volatile memory transistor and the second drain region of the second non-volatile memory transistor.
3. The non-volatile memory array of claim 1 , further comprising:
a first word line coupled to a control gate of the first non-volatile memory transistor; and
a second word line coupled to a control gate of the second non-volatile memory transistor; and
a source select line coupled to a gate of the source access transistor.
4. The non-volatile memory array of claim 3 , wherein the first word line, the second word line and the source select line extend in parallel along a first axis.
5. The non-volatile memory array of claim 1 , wherein the only transistors in each EEPROM cell pair are the first non-volatile memory transistor, the second non-volatile memory transistor and the source access transistor.
6. A non-volatile memory array comprising:
one or more electrically erasable and programmable memory (EEPROM) cell pairs, each configured to store two data bits, and including:
a first non-volatile memory transistor having a first source region;
a second non-volatile memory transistor having a second source region; and
a source access transistor that shares the first source region with the first non-volatile memory transistor, and shares the second source region with the second non-volatile memory transistor, wherein the source access transistor comprises a floating gate electrode and a control gate electrode.
7. A non-volatile memory array comprising:
one or more electrically erasable and programmable memory (EEPROM) cell pairs, each configured to store two data bits, and including:
a first non-volatile memory transistor;
a second non-volatile memory transistor; and
a source access transistor, having a first semiconductor region continuous with a source region of the first non-volatile memory transistor, a second semiconductor region continuous with a source region of the second non-volatile memory transistor, and a third semiconductor region that extends downward through a first well region to contact a second well region, wherein the first, second and third semiconductor regions and the second well region have a first conductivity type, and the first well region has a second conductivity type, opposite the first conductivity type.
8. The non-volatile memory array of claim 7 , further comprising a bit line coupled to a drain of the first non-volatile memory transistor and a drain of the second non-volatile memory transistor.
9. The non-volatile memory array of claim 7 , further comprising:
a first word line coupled to a control gate of the first non-volatile memory transistor; and
a second word line coupled to a control gate of the second non-volatile memory transistor; and
a source select line coupled to a gate of the source access transistor.
10. The non-volatile memory array of claim 9 , wherein the first word line, the second word line and the source select line extend in parallel along a first axis.
11. The non-volatile memory array of claim 7 , wherein the source access transistor comprises a floating gate electrode and a control gate electrode.
12. The non-volatile memory array of claim 7 , wherein the only transistors in each EEPROM cell pair are the first non-volatile memory transistor, the second non-volatile memory transistor and the source access transistor.
13. A non-volatile memory array comprising:
one or more electrically erasable and programmable memory (EEPROM) cell pairs, each configured to store two data bits, and including:
a first non-volatile memory transistor having a first source region;
a second non-volatile memory transistor having a second source region; and
a source access transistor that shares the first source region with the first non-volatile memory transistor, and shares the second source region with the second non-volatile memory transistor,
wherein the first non-volatile memory transistor, the second non-volatile memory transistor and the source access transistor are located in a first well region having a first conductivity type, wherein the first source region and the second source region have a second conductivity type, opposite the first conductivity type.
14. The non-volatile memory array of claim 13 , wherein the source access transistor further includes one or more regions of the second conductivity type that extend through the first well region to contact a second well region of the second conductivity type, wherein the first well region is located in the second well region.
15. The non-volatile memory array of claim 13 , further comprising a bit line coupled to a drain of the first non-volatile memory transistor and a drain of the second non-volatile memory transistor.
16. The non-volatile memory array of claim 13 , further comprising:
a first word line coupled to a control gate of the first non-volatile memory transistor;
a second word line coupled to a control gate of the second non-volatile memory transistor; and
a source select line coupled to a gate of the source access transistor.
17. The non-volatile memory array of claim 16 , wherein the first word line, the second word line and the source select line extend in parallel along a first axis.
18. The non-volatile memory array of claim 13 , wherein the source access transistor comprises a floating gate electrode and a control gate electrode.
19. The non-volatile memory array of claim 13 , wherein the only transistors in each EEPROM cell pair are the first non-volatile memory transistor, the second non-volatile memory transistor and the source access transistor.
20. A non-volatile memory array comprising:
one or more electrically erasable and programmable memory (EEPROM) cell pairs, each configured to store two data bits, and including:
a first non-volatile memory transistor having a first source region;
a second non-volatile memory transistor having a second source region; and
a source access transistor that shares the first source region with the first non-volatile memory transistor, and shares the second source region with the second non-volatile memory transistor,
wherein the first non-volatile memory transistor, the second non-volatile memory transistor and the source access transistor have gate structures with identical layers.