Automatic generating of timing constraints for the validation/signoff of test structures
View Patent ↗An apparatus comprising a database, an input module and a software tool. The database may be configured to generate one or more database files representing a design of an integrated circuit (IC). The input module may be configured to generate one or more test structures to test predetermined portions of the design of an IC. The software tool may be configured to automatically generate test scripts to verify timing constraints of the one or more test structures.
1. An apparatus comprising:
a database configured to generate one or more database files representing a design of an integrated circuit (IC);
an input module comprising a test insertion application configured to generate one or more test structures and simulation vectors to test predetermined portions of said design of an IC; and
a software tool configured to automatically (i) generate test scripts to setup and control a static timing analysis (STA) tool to verify timing constraints of said one or more test structures and (ii) report only those timing issues relevant to the one or more test structures by filtering false timing violations reported by the STA tool, wherein said software tool (A) reads and extracts information about the one or more test structures from the test insertion application tightly linked to the generation of simulation vectors for the one or more test structures and utilizes a pre-layout netlist of a test access port (TAP) controller to define pre-layout registers and port associations of the test access port and (B) is further configured to automatically (i) merge timing constraints of overlapping logic between said tests structures and a functional portion of said IC and (II) generate said scripts to verify timing constraints of said overlapping logic between said test structures and said functional portion of said IC.
2. The apparatus according to claim 1 , wherein said input module generates said test structures via high level commands that invoke third party tools.
3. The apparatus according to claim 1 , wherein said software tool determines a design class for said design of an IC.
4. The apparatus according to claim 3 , wherein said test scripts are divided into two parts comprising (i) a first set of test scripts which are common to all selected test structures and (ii) a second set of test scripts which are specific to each selected test structure.
5. The apparatus according to claim 4 , wherein said first set of test scripts executes instructions related to an application specific integrated circuit (ASIC) design class.
6. The apparatus according to claim 4 , wherein said first set of test scripts executes instructions related to a structured/platform ASIC design class.
7. The apparatus according to claim 4 , wherein said second set of scripts executes instructions specific to each of said selected test structures.
8. The apparatus according to claim 1 , wherein said input module further comprises a test insertion application configured to generate and insert said one or more test structures into said design.
9. The apparatus according to claim 1 , wherein said software tool is further configured to automatically analyze one or more reports generated by said STA tool.
10. The apparatus according to claim 1 , wherein said software tool generates said test scripts based upon one or more types of information selected from the group consisting of a post-test chip-level netlist, names of Scanln/Out pins, instructions to be loaded into a test access port (TAP) controller instruction-register to setup the design in a desired test mode configuration and timing information about signoff simulation vectors.
11. The apparatus according to claim 10 , wherein said timing information about signoff simulation vectors comprises one or more of clock tree synthesis information, worst case delay information and best case delay information.
12. The apparatus according to claim 1 , wherein said software tool is further configured to (i) determine real signal sources of TAP ports and (ii) move STA constraints to locations in said design that are preserved during a layout flow.
13. An apparatus comprising:
means for generating one or more database files representing a design of an integrated circuit (IC);
means for generating one or more test structures and simulation vectors to test predetermined portions of said design of an IC; and
means for automatically (i) generating test scripts to setup and control a static timing analysis (STA) tool to verify timing constraints of said one or more test structures and (ii) report only those timing issues that are relevant to the one or more test structures by filtering false timing violations reported by the STA tool; means for reading and extracting information about the one or more test structures from test insertion application tightly linked to the generation of simulation vectors for the one or more test structures and utilizes a pre-layout netlist of a test access Port (TAP) controller to define pre-layout registers and port associations of the test access port and means for automatically (i) merging timing constraints of overlapping logic between said test structures and a functional portion of said IC and (ii) generating said test scripts to verify timing constraints of said overlapping between said test structures and functional portion of said IC.
14. A method for verifying timing constraints of test structures in an electronic design automation (EDA) test tool, comprising the steps of:
(A) generating one or more database files representing a design of an integrated circuit (IC);
(B) generating said test structures and simulation vectors to test predetermined portions of said design of an IC; and
(C) automatically (i) generating test scripts to setup and control a static timing analysis (STA) tool to verify timing constraints of said test structures and (ii) reporting only those timing issues relevant to said test structures by filtering false timing violations reported by the STA tool, wherein information about the one or more test structures tightly linked to the generation of the simulation vectors for the test structures is read and extracted from a test insertion application and a pre-layout netlist of a test access port (TAP) controller is utilized to define pre-layout registers and port associations of the test access port and (D) automatically (i) merging timing constraintsof overlapping logic between said test structures and a functional portion of said IC and (ii) generating said test scripts to verify timing.
15. The method according to claim 14 wherein step (C) further comprises the step of:
selecting test structures via user commands.
16. The method according to claim 15 , further comprising the step of:
assessing a design class for said integrated circuit design.
17. The method according to claim 15 , further comprising the step of: dividing said test scripts into (i) a first set of test scripts which are common to all selected test structures and (ii) a second set of test scripts which are specific to each of said selected test structures.
18. The method according to claim 17 , further comprising the step of:
executing instructions in said first set of test scripts related to an application specific integrated circuit (ASIC) design class.
19. The method according to claim 17 , further comprising the step of:
executing instructions in said first set of test scripts related to a structured/platform ASIC design class.
20. The method according to claim 17 , further comprising the step of: executing instructions in said second set of scripts specific to each of said selected test structures.