TFT mask ROM and method for making same

1. A TFT mask ROM array, comprising:

a first plurality of spaced apart conductor rails disposed at a first height above a substrate in a first direction;

a second plurality of spaced apart rail stacks disposed at a second height in a second direction different from the first direction, each rail stack including:

a first semiconductor layer whose first surface is in contact with said first plurality of spaced apart conductor rails;

a conductive film; and

a gate insulating film disposed between a second surface of the first semiconductor layer and the conductive film;

wherein TFTs are formed at intersections of two adjacent conductor rails and one rail stack; and

wherein the TFTs comprise a first set of enabled TFTs and a second set of partially or totally disabled TFTs.

2. The array of claim 1 , wherein:

the first plurality of rails comprise polysilicon layers of a first conductivity type in contact with metal or a metal silicide layers;

the first semiconductor layer comprises a polysilicon layer;

the gate insulating layer comprises a portion of a charge storage region; and the conductive film comprises a polysilicon layer and a metal suicide layer.

3. The array of claim 2 , wherein:

the polysilicon layers of the first rails comprise at least a portion of the TFT source and drain regions;

the conductive film comprises a gate of the TFTs;

portions of the first semiconductor layer comprise TFT channel regions of a second conductivity type; and

the charge storage region comprises a dielectric isolated floating gate, an ONO dielectric film or an insulating layer containing conductive nanocrystals.

4. The array of claim 3 , further comprising:

doped regions of a first conductivity type in the first semiconductor layer comprising portions of the source and drain regions;

a first insulating layer located between the first rails; and

a second insulating layer located between the second rail stacks.

5. The array of claim 2 , wherein the first rails are located below the second rail stacks.

6. The array of claim 2 , wherein the first rails are located above the second rail stacks.

7. The array of claim 1 , wherein the second set of TFTs comprises a set of totally disabled TFTs.

8. The array of claim 1 , wherein the second set of TFTs comprises a plurality of totally disabled TFTs and a plurality of partially disabled TFTs.

9. The array of claim 1 , wherein at least a portion of channel regions of the partially or totally disabled TFTs of the second set have been selectively removed.

10. The array of claim 1 , wherein at least a portion of channel regions of the partially or totally disabled TFTs of the second set have been selectively doped to increase a threshold voltage of said TFTs to render said TFTs partially or totally inoperative.

11. A monolithic three dimensional TFT mask ROM array, comprising a plurality of device levels, each device level comprising the array of claim 1 .